參數(shù)資料
型號: AD9215BRUZRL7-80
廠商: Analog Devices Inc
文件頁數(shù): 19/36頁
文件大小: 0K
描述: IC ADC 10BIT 80MSPS 3V 28TSSOP
設(shè)計資源: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Interfacing the High Frequency AD8331 to AD9215 (CN0096)
標準包裝: 1,000
位數(shù): 10
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 104mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
配用: AD9215BCP-80EBZ-ND - BOARD EVAL FOR AD9215BCP-80
AD9215BCP-65EBZ-ND - BOARD EVAL FOR AD9215BCP-65
AD9215BCP-105EBZ-ND - BOARD EVAL FOR AD9215BCP-105
AD9215
Data Sheet
Rev. B | Page 26 of 36
02874-A
-048
ORX
D5X
D6X
D7X
D8X
D9X
+
AGND
VIN+
AVDD
CLK
MODE
OR
PWDN
REFB
REFT
SENSE
VREF
VIN–
AGND
AVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DRGND
DRVDD
DNC
PRI
SEC
CD
B
A
MODE
SELECT
F
G
E
H
MODE
SELECT
CONFIGURATION
E:2C/DCS
OFF
F:2C/DCS
ON
G:OB/DCS
ON
H:OB/DCS
OFF
(LSB)
(MSB)
OPTIONAL
DIFFERENTIAL
INPUT
ANALOG
INPUT
OPTIONS
1.
R6,
R34
FOR
DIFFERENTIAL
OPERATION
2.
C1,
C33
FOR
OP
AMP
OPERATION
3.
R7,
R46,
R5,
C9,
C23
FOR
SINGLE-ENDED
OPERATION
COMMON
MODE
PLEASE
JUMPER
E45
TO
E32
DC
VOLTAGE
ADJUST
OR
JUMPER
E45
TO
E12
CAPACITOR
TO
GROUND
OVERRANGE
BIT
E9
E11
GND
AVDD
AIN
AMP
J1
L1
10nH
GND
AVDD
E19
E16
E17
SENSE
GND
VREF
OR1
8
9
7
13
2
1
14
5
6
3
4
10
11
12
17
18
19
20
21
22
25
26
27
28
23
24
16
15
DEVICE
=
AD9215
U1
PARTS
=
1
C29
10
F
AMPIN
GND
AVDD
GND
AVDD
1
5
34
2
6
T1
GND
9
10
12
13
14
15
2
3
4
5
6
7
8
1
16
11
CLK
GND
E7
E8
E2
E5
E21
E20
E18
E22
E23
AVDD
E1
E3
E4
E6
2
3
4
5
6
7
8
1
9
10
12
13
14
15
16
11
E45
E12
COM
GND
3.0V
5.0V
2.5V
3.0V
VDL
13
24
P2
13
24
VAMP
GND
VCLK
GND
DRVDD
AVDD
GND
DRVDD
GND
NCX
D4X
D3X
D2X
D1X
D0X
NC2X
GND
AVDD
GND
DRVDD
VDL
E29
E28
E27
E26
E25
E24
VCLK
AVDD
GND
REFERENCE
CONFIGURATION
A:
EXTERNAL
VOLTAGE
DIVIDER
REFERENCE
B:
INTERNAL
1V
REFERENCE
C:
EXTERNAL
REFERENCE
D:
INTERNAL
0.5V
REFERENCE
1V
MAX
SINGLE-ENDED
INPUT
OPERATION
1.
PLACE
R7(
50
),
R5(
0
)AND
R46
(25
)
2.
PLACE
C23
(0.1
F),
C9
(0.1
F)
3.
REMOVE
C33,
C1,
R34,
R6,
C32
RP2
220
RP1
220
R11
1k
R29
1k
R24
1k
R21
33
R19
33
R44
1k
R45
1k
R34
0
R6
0
R25
25
R32
36
R33
36
R5
0
R16
XX
R8
1k
R10
1k
R9
1k
R4
10k
R15
10k
R7
50
C32
0.1
F
C7
0.001
F
C9
0.1
F
C6
0.1
F
C16
0.1
F
C13
0.1
F
C15
0.1
F
OPTIONAL
E32
GND
AVDD
GND
R3
5k
R1
10
C14
0.1
F
C12
0.1
F
C23
0.1
F
C11
0.1
F
C5
10pF
C8
10pF
C18
0.1
F
C30
0.1
F
C52
10
F
C17
0.1
F
Figure 50. TSSOPP Evaluation Board Schematic, Analog Inputs and DUT
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