參數(shù)資料
型號： AD9215BCP-105EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/36頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9215BCP-105
設計資源： Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Interfacing the High Frequency AD8331 to AD9215 (CN0096)
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： 1 Vpp
在以下條件下的電源（標準）： 120mW @ 105MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9215-105
已供物品： 板
相關產品： AD9215BRUZ-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP
AD9215BRUZ-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP
AD9215BRUZRL7-105-ND - IC ADC 10BIT 105MSPS 3V 28TSSOP
AD9215BRUZRL7-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP
AD9215BRUZRL7-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP
AD9215BRUZ-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP
AD9215BCPZ-105-ND - IC ADC 10BIT 105MSPS 3V 32-LFCSP
AD9215BRU-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP
AD9215BCPZ-80-ND - IC ADC 10BIT 80MSPS 32LFCSP
AD9215BCPZ-65-ND - IC ADC 10BIT 65MSPS 32-LFCSP
更多...
Data Sheet
AD9215
Rev. B | Page 17 of 36
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately one second to fully discharge
the reference buffer decoupling capacitors and 7 ms to restore
full operation.
Digital Outputs
The AD9215 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
Timing
The AD9215 provides latched data outputs with a pipeline delay
of five clock cycles. Data outputs are available one propagation
delay (tOD) after the rising edge of the clock signal. Refer to Fig-
ure 2 for a detailed timing diagram.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9215;
these transients can detract from the converter’s dynamic per-
formance.
The lowest typical conversion rate of the AD9215 is 5 MSPS. At
clock rates below 5 MSPS, dynamic performance may degrade.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9215. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9215, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. Max-
imum SNR and DNL performance is achieved with the AD9215
set to the largest input span of 2 V p-p.
Internal Reference Connection
A comparator within the AD9215 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 1
. If SENSE is grounded,
the reference amplifier switch is connected to the internal resis-
tor divider (see Figure 36), setting VREF to 1 V. Connecting the
SENSE pin to the VREF pin switches the amplifier output to the
SENSE pin, configuring the internal op amp circuit as a voltage
follower and providing a 0.5 V reference output. If an external
resistor divider is connected as shown in Figure 37, the switch is
again set to the SENSE pin. This puts the reference amplifier in a
noninverting mode with the VREF output defined as
R1
R2
VREF
1
5
.
0
02874-A
-034
10
F
+
0.1
F
VREF
SENSE
0.5V
7k
7k
AD9215
VIN–
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
Figure 36. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the ADC
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
02874-A-035
10
F
+
0.1
F
VREF
R2
R1
SENSE
0.5V
AD9215
VIN–
VIN+
REFT
0.1
F
0.1
F
10
F
0.1
F
REFB
SELECT
LOGIC
ADC
CORE
Figure 37. Programmable Reference Configuration
If the internal reference of the AD9215 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 38 de-
picts how the internal reference voltage is affected by loading.
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相關代理商/技術參數(shù)
參數(shù)描述
AD9215BCP-65 制造商:Analog Devices 功能描述:ADC Single Pipelined 65Msps 10-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT LOW POWER 65/80/105 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:10BIT ADC 65MSPS 9215 LFCSP-32
AD9215BCP-65EB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk
AD9215BCP-65EBZ 功能描述:BOARD EVAL FOR AD9215BCP-65 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
AD9215BCP-80 制造商:Analog Devices 功能描述:ADC Single Pipelined 80Msps 10-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT LOW POWER 65/80/105 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:10BIT ADC 80MSPS 9215 LFCSP-32
AD9215BCP-80EB 制造商:Analog Devices 功能描述:Evaluation Board For AD9215 3 V A/D Converter ,10-Bit, 65/80/105 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk
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