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參數(shù)資料
| 型號(hào)： | AD9215BCP-105EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9215BCP-105 |
| 設(shè)計(jì)資源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) Interfacing the High Frequency AD8331 to AD9215 (CN0096) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | 1 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 120mW @ 105MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9215-105 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9215BRUZ-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP AD9215BRUZ-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP AD9215BRUZRL7-105-ND - IC ADC 10BIT 105MSPS 3V 28TSSOP AD9215BRUZRL7-65-ND - IC ADC 10BIT 65MSPS 3V 28TSSOP AD9215BRUZRL7-80-ND - IC ADC 10BIT 80MSPS 3V 28TSSOP AD9215BRUZ-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP AD9215BCPZ-105-ND - IC ADC 10BIT 105MSPS 3V 32-LFCSP AD9215BRU-105-ND - IC ADC 10BIT 105MSPS 3V 28-TSSOP AD9215BCPZ-80-ND - IC ADC 10BIT 80MSPS 32LFCSP AD9215BCPZ-65-ND - IC ADC 10BIT 65MSPS 32-LFCSP 更多... |
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AD9215
Data Sheet
Rev. B | Page 18 of 36
02874-A-036
ILOAD (mA)
VREF
ERROR
(%)
0
0.05
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
VREF = 0.5V
VREF = 1.0V
Figure 38. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. When multiple ADCs track one another, a single refer-
ence (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 39 shows the typical drift characteris-
tics of the internal reference in both 1 V and 0.5 V modes.
02874-A-037
TEMPERATURE (
°C)
VREF
ERROR
(%)
0.4
0.5
0.6
0.3
0.2
0.1
0
–40
–20
0
20
40
60
80
VREF = 1.0V
VREF = 0.5V
Figure 39. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
Operational Mode Selection
As discussed earlier, the AD9215 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. For best ac performance, enabling the duty cycle
stabilizer is recommended for all applications. The input
threshold values and corresponding mode selections are out-
lined in Table 9.
As detailed in Table 9, the data format can be selected for either
offset binary or twos complement.
Table 9. Mode Selection
MODE Voltage
Data Format
Duty Cycle Stabilizer
AVDD
Twos Complement
Disabled
2/3 AVDD
Twos Complement
Enabled
1/3 AVDD
Offset Binary
Enabled
AGND (Default)
Offset Binary
Disabled
The MODE pin is internally pulled down to AGND by a 20 k
resistor.
EVALUATION BOARD
The AD9215 evaluation board is no longer in production. The
following evaluation board documentation is provided for in-
formational purposes only.
The AD9215 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through an AD8351 driver, a transformer, or single-ended. Sep-
arate power pins are provided to isolate the DUT from the sup-
port circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 40 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9215. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be
used to realize the ultimate performance of the converter. Prop-
er filtering of the input signal, to remove harmonics and lower
the integrated noise at the input, is also necessary to achieve the
specified noise performance.
Complete schematics and layout plots follow that demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
02874-A-038
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
R AND S SMG, 2V p-p
SIGNAL SYNTHESIZER
REFIN
10MHz
REFOUT
BAND-PASS
FILTER
3.0V
–
+
–
+
–
+
–
+
2.5V
5.0V
AVDD
DRVDD
GND
GND VDL
VAMP
XFMR
INPUT
CLK
P12
AD9215
EVALUATION BOARD
DATA
CAPTURE
AND
PROCESSING
2.5V
Figure 40. Evaluation Board Connections
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9215BCP-65 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 65Msps 10-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT LOW POWER 65/80/105 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:10BIT ADC 65MSPS 9215 LFCSP-32 |
| AD9215BCP-65EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk |
| AD9215BCP-65EBZ | 功能描述:BOARD EVAL FOR AD9215BCP-65 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9215BCP-80 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 80Msps 10-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT LOW POWER 65/80/105 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:10BIT ADC 80MSPS 9215 LFCSP-32 |
| AD9215BCP-80EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9215 3 V A/D Converter ,10-Bit, 65/80/105 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk |
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