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| 型號(hào)： | AD9212BCPZRL7-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 8-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁(yè)數(shù)： | 33/56頁(yè) |
| 文件大?。?/td> | 1840K |
| 代理商： | AD9212BCPZRL7-40 |
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AD9212
Table 15. Memory Map Register
Rev. 0 | Page 33 of 56
Addr.
(Hex)
Chip Configuration Registers
00
chip_port_config
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default Notes/
Comments
0
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0
0x18
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode registers
correctly
regardless of
shift mode.
Default is unique
chip ID, different
for each device.
This is a read-
only register.
Child ID used to
differentiate
graded devices.
01
chip_id
10-bit Chip ID Bits 7:0
(AD9212 = 0x08), (default)
Read
only
02
chip_grade
X
Child ID 6:4
(identify device variants of Chip ID)
000 = 65 MSPS
001 = 40 MSPS
X
X
X
X
Read
only
Device Index and Transfer Registers
04
device_index_2
X
X
X
X
Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
D
1 = on
(default)
0 = off
X
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
X
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
X
Data
Channel
E
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
05
device_index_1
X
X
Clock
Channel
DCO
1 = on
0 = off
(default)
X
Clock
Channel
FCO
1 = on
0 = off
(default)
X
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
FF
device_update
X
X
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08
modes
X
X
X
X
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
X
X
0x00
Determines
various generic
modes of chip
operation.
09
clock
X
X
X
X
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01
Turns the
internal duty
cycle stabilizer
on and off.
0D
test_io
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see Table 9 in the
Digital Outputs and Timing section
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = user input
1001 = one/zero bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
0x00
When set, the
test data is
placed on the
output pins in
place of normal
data.
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