參數(shù)資料
型號: AD9212BCPZRL7-40
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述: 8-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC64
封裝: 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù): 10/56頁
文件大小: 1840K
代理商: AD9212BCPZRL7-40
AD9212
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 10 of 56
PIN 1
INDICATOR
1
D
1
D
1
D
2
D
2
D
2
D
2
D
2
D
2
F
2
F
2
D
2
D
2
D
3
D
3
D
3
D
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
V
V
A
V
V
A
R
R
V
S
R
V
V
A
V
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD
VIN+G
VIN–G
AVDD
VIN–H
VIN+H
AVDD
AVDD
CLK–
CLK+
AVDD
AVDD
DRGND
DRVDD
D–H
D+H
AVDD
VIN+B
VIN–B
AVDD
VIN–A
VIN+A
AVDD
PDWN
CSB
SDIO/ODM
SCLK/DTP
AVDD
DRGND
DRVDD
D+A
D–A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9212
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
0
Figure 5. 64-Lead LFCSP Top View
Table 7. Pin Function Descriptions
Pin No.
0
1, 4, 7, 8, 11,
12, 37, 42, 45,
48, 51, 59, 62
13, 36
14, 35
2
3
5
6
9
10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
AGND
AVDD
Description
Analog Ground (Exposed Paddle)
1.8 V Analog Supply
DRGND
DRVDD
VIN+G
VING
VINH
VIN+H
CLK
CLK+
DH
D+H
DG
D+G
DF
D+F
DE
D+E
DCO
DCO+
FCO
FCO+
DD
D+D
DC
D+C
DB
D+B
Digital Output Driver Ground
1.8 V Digital Output Driver Supply
ADC G Analog Input—True
ADC G Analog Input—Complement
ADC H Analog Input—Complement
ADC H Analog Input—True
Input Clock—Complement
Input Clock—True
ADC H Digital Output—Complement
ADC H True Digital Output—True
ADC G Digital Output—Complement
ADC G True Digital Output—True
ADC F Digital Output—Complement
ADC F True Digital Output—True
ADC E Digital Output—Complement
ADC E True Digital Output—True
Data Clock Digital Output—Complement
Data Clock Digital Output—True
Frame Clock Digital Output—Complement
Frame Clock Digital Output—True
ADC D Digital Output—Complement
ADC D True Digital Output—True
ADC C Digital Output—Complement
ADC C True Digital Output—True
ADC B Digital Output—Complement
ADC B True Digital Output—True
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