參數(shù)資料
型號(hào)： AD9212BCPZ-65
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述： 8-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁(yè)數(shù)： 26/56頁(yè)
文件大小： 1840K
代理商： AD9212BCPZ-65
AD9212
Two output clocks are provided to assist in capturing data from
the AD9212. The DCO is used to clock the output data and is
equal to five times the sampling clock (CLK) rate. Data is
clocked out of the AD9212 and must be captured on the rising
and falling edges of the DCO that supports double data rate
Rev. 0 | Page 26 of 56
(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.
Table 9. Flex Output Test Modes
Output Test
Mode Bit
Sequence
0000
0001
Pattern Name
Off (default)
Midscale short
Digital Output Word 1
N/A
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A
N/A
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
Register 0x19 to Register 0x1A
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1010 0011 (8-bit)
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
Digital Output Word 2
N/A
Same
Subject
to Data
Format
Select
N/A
Yes
0010
+Full-scale short
Same
Yes
0011
Full-scale short
Same
Yes
0100
Checker board
0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
N/A
N/A
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
Register 0x1B to Register 0x1C
N/A
No
0101
0110
0111
PN sequence long
1
PN sequence short
1
One/zero word toggle
Yes
Yes
No
1000
1001
User input
One/zero bit toggle
No
No
1010
1× sync
N/A
No
1011
One bit high
N/A
No
1100
Mixed frequency
N/A
No
1
PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is
9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1
(short), defines the pseudorandom sequence.
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