參數(shù)資料
型號: AD9212BCPZ-40
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述: 8-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC64
封裝: 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù): 31/56頁
文件大?。?/td> 1840K
代理商: AD9212BCPZ-40
AD9212
Rev. 0 | Page 31 of 56
0
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 71. SDIO Pin Loading
V
O
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0
30
20
10
40
50
60
70
80
90
100
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
0
Figure 72. Serial Timing Details
Table 14. Serial Timing Definitions
Parameter
t
DS
t
DH
t
CLK
t
S
t
H
t
HI
t
LO
t
EN_SDIO
Timing (minimum, ns)
5
2
40
5
2
16
16
1
Description
Set-up time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Set-up time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 72)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 72)
t
DIS_SDIO
5
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