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參數(shù)資料
| 型號(hào)： | AD9212BCPZ-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 8-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 23/56頁 |
| 文件大?。?/td> | 1840K |
| 代理商： | AD9212BCPZ-40 |
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AD9212
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
A
) due only to aperture jitter (t
J
) can be calculated by
SNR degradation
= 20 × log 10 [1/2 × π ×
f
A
×
t
J
]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 56).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9212.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note
and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit
www.analog.com
).
Rev. 0 | Page 23 of 56
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
0
Figure 56. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 57 and Figure 58, the power dissipated by
the AD9212 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
0
0
0.05
0.10
0.15
0.20
0.25
0.30
10
15
20
25
30
35
40
ENCODE (MHz)
C
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
P
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
Figure 57. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, AD9212-40
0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
10
20
30
40
50
60
ENCODE (MHz)
C
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
P
TOTAL POWER
AVDD CURRENT
DRVDD CURRENT
Figure 58. Supply Current vs. f
SAMPLE
for f
IN
= 10.3 MHz, AD9212-65
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9212BCPZ-65 | Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9212BCPZRL7-40 | Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9212BCPZRL7-65 | Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9214 | 10-Bit, 65/80/105 MSPS 3 V A/D Converter |
| AD9214-105PCB | 10-Bit, 65/80/105 MSPS 3 V A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9212BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 65Msps 10-bit Serial 64-Pin LFCSP EP |
| AD9212BCPZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9212BCPZRL7-65 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9214 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 65/80/105 MSPS 3 V A/D Converter |
| AD9214-105PCB | 制造商:Analog Devices 功能描述:10 BIT 105MSPS A/D CONV. EVAL BOARD - Bulk |
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