參數(shù)資料
型號(hào)： AD9212-65EBZ
廠商： Analog Devices, Inc.
英文描述： Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述： 八路，10位，六十五分之四十〇 MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器
文件頁(yè)數(shù)： 21/56頁(yè)
文件大?。?/td> 1840K
代理商： AD9212-65EBZ
AD9212
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates the positive and negative reference voltages, REFT
and REFB, respectively, that define the span of the ADC core.
The output common mode of the reference buffer is set to
midsupply, and the REFT and REFB voltages and span are
defined as
REFT
= 1/2 (
AVDD
+
VREF
)
REFB
= 1/2 (
AVDD
VREF
)
Span
= 2 × (
REFT
REFB
) = 2 ×
VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is always achieved by setting the
ADC to the largest span in a differential configuration. In the
case of the AD9212, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways in which to drive the AD9212 either
actively or passively. In either case, the optimum performance is
achieved by driving the analog input differentially. One example
is by using the AD8334 differential driver. It provides excellent
performance and a flexible interface to the ADC (see Figure 50)
for baseband applications. This configuration is common for
medical ultrasound systems.
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9212. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. Two
examples are shown in Figure 47 and Figure 48.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
Rev. 0 | Page 21 of 56
2Vp-p
R
R
C
DIFF1
C
1
C
DIFF
IS OPTIONAL.
49.9
0.1
μ
F
1k
1k
AGND
AVDD
ADT1–1WT
1:1 Z RATIO
VIN–
ADC
AD9212
VIN+
C
0
Figure 47. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9212
VIN–
2Vp-p
2.2pF
33
1k
0.1
μ
F
1k
1k
AVDD
ADT1–1WT
1:1 Z RATIO
16nH
16nH
0.1
μ
F
16nH
33
499
65
VIN+
0
Figure 48. Differential Transformer-Coupled Configuration for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+
pin while the VIN pin is terminated. Figure 49 details a typical
single-ended input configuration.
2V p-p
R
R
49.9
0.1μF
0.1μF
AVDD
1k
25
1k
1k
AVDD
VIN–
ADC
AD9212
VIN+
C
DIFF1
C
1
C
DIFF
IS OPTIONAL.
C
0
Figure 49. Single-Ended Input Configuration
AD8334
1.0k
1.0k
374
187
R
R
C
0.1
μ
F
187
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
1V p-p
0.1
μ
F
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF
274
VIN–
ADC
AD9212
VIN+
VREF
0
Figure 50. Differential Input Configuration Using the AD8334
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