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參數(shù)資料
| 型號(hào)： | AD9203ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大?。?/td> | 216K |
| 代理商： | AD9203ARU |
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REV. 0
AD9203
–14–
POWER CONTROL
Power consumed by the AD9203 may be reduced by placing a
resistor between the PWRCON pin and ground. This function
will be valuable to users who do not need the AD9203’s high
conversion rate, but do need even lower power consumption.
The external resistor sets the programming of the analog current
mirrors. Table II illustrates the relationship between programmed
power and performance.
At lower clock rates, less power is required within the analog
sections of the AD9203. Placing an external resistor on the
PWRCON pin will shunt control current away from some of the
current mirrors. This enables the ADC to convert low data rates
with extremely low power consumption.
INTERFACING TO 5 V SYSTEMS
The AD9203 can be integrated into +5 V systems. This is
accomplished by deriving a 3 V power supply from the existing
5 V analog power line through an AD3307-3 linear regulator.
Care must be maintained so that logic inputs do not exceed the
maximum rated values listed on the Specifications page.
CLOCK INPUT AND CONSIDERATIONS
The AD9203 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. Sampling
occurs on the falling edge. The clock input to the AD9203
operating at 40 MSPS may have a duty cycle between 45% to
55% to meet this timing requirement since the minimum speci-
fied t
CH
and t
CL
is 11.25 ns. For clock rates below 40 MSPS, the
duty cycle may deviate from this range to the extent that both
t
CH
and t
CL
are satisfied. See Figure 29 for dynamics vs. duty
cyle.
High speed high resolution A/Ds are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
IN
) due only to aperture jitter (t
A
) can be
calculated with the following equation:
SNR degradation
= 20 log
10
[1/2
π
f
IN
t
A
]
In the equation, the rms aperture jitter,
t
A
, represents the root-
sum square of all the jitter sources, which include the clock in-
put, analog input signal, and A/D aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
Clock input should be treated as an analog signal in cases where
aperture jitter may affect the dynamic range of the AD9203.
Power supplies for clock drivers should be separated from the
A/D output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing or other method), it should
be retimed by the original clock at the last step.
The clock input is referred to the analog supply. Its logic thresh-
old is AVDD/2.
DIGITAL INPUTS AND OUTPUTS
Each of the AD9203 digital control inputs, 3-STATE, DFS and
STBY are referenced to analog ground. CLK is also referenced
to analog ground. A low power mode feature is provided such
that for STBY = HIGH and the static power of the AD9203 drops
to 0.65 mW.
Asserting the DFS pin high will invert the MSB pin, changing
the data to a twos complement format.
The AD9203 has an OTR (out of range) function. If the input
voltage is above or below full scale by 1 LSB, the OTR flag will
go high. See Figure 30.
+FS
–FS
OTR
DATA OUTPUTS
1
0
0
11111
11111
11111
11111
11111
11110
0
0
1
00000
00000
00000
00001
00000
00000
OTR
+FS – 1 LSB
–FS + 1 LSB
Figure 30. Output Data Format
Table II. Power Programming Resistance
Total Power
Into 5 pF Load
mW
Power Control
Resistor
k
V
Clock
MHz
f
IN
MHz
THD
dB
SNR
dB
SINAD
dB
SFDR
dB
IAVDD
mA
IDRVDD
mA
5
10
15
20
30
2.5
2.5
2.5
5
5
–72
–74.3
–74
–75.1
–75
60.6
60.7
60.1
53.4
59.5
59.9
60.4
59.9
53.2
59.4
77.9
77.8
77.7
78.9
74.8
5.0
5.9
6.7
7.8
10
0.86
1.2
1.8
2.4
4.0
17
21.3
25
30
42
37
37
37
50
50
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| AD9203ARUZ | 功能描述:IC ADC 10BIT 40MSPS 3V 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤(pán)（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9203ARUZ | 制造商:Analog Devices 功能描述:IC ADC 10BIT 40MSPS 28TSSOP |
| AD9203ARUZ | 制造商:Analog Devices 功能描述:IC, ADC, 10BIT, 40MSPS, TSSOP-28 |
| AD9203ARUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter |
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