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| 型號(hào)： | AD9203ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大小： | 216K |
| 代理商： | AD9203ARU |
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REV. 0
AD9203
–12–
DRIVING THE ANALOG INPUT
Figure 23 illustrates the equivalent analog input of the AD9203,
(a switched capacitor input). Bringing CLK to a logic high,
opens S3 and closes S1 and S2. The input source connected
to AIN and must charge Capacitor C
H
during this time. Bring-
ing CLK to a logic low opens S2, and then S1 opens followed
by closing S3. This puts the input in the hold mode.
C
P
S2
S3
S1
C
P
AD9203
C
H
C
H
Figure 23. Input Architecture
The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance,
C
P
, and the hold capacitance, C
H
, is typically less than 5 pF.
The input source must be able to charge or discharge this ca-
pacitance to 10-bit accuracy in one half of a clock cycle. When
the SHA goes into track mode, the input source must charge or
discharge capacitor C
H
from the voltage already stored on C
H
to
the new voltage. In the worst case, a full-scale voltage step on
the input source must provide the charging current through the
R
ON
(100
) of Switch 1 and quickly (within 1/2 CLK period)
settle. This situation corresponds to driving a low input imped-
ance. Adding series resistance between the output of the signal
source and the AIN pin reduces the drive requirements placed
on the signal source. Figure 24 shows this configuration. The
bandwidth of the particular application limits the size of this
resistor. To maintain the performance outlined in the data sheet
specifications, the resistor should be limited to 50
or less. The
series input resistor can be used to isolate the driver from the
AD9203’s switched capacitor input. The external capacitor may
be selected to limit the bandwidth into the AD9203. Two input
RC networks should be used to balance differential input drive
schemes (Figure 24).
The input span of the AD9203 is a function of the reference
voltage. For more information regarding the input range, see the
Internal and External Reference sections of the data sheet.
AIN
V
S
<50
V
AD9203
Figure 24. Simple AD9203 Drive Configuration
In many cases, particularly in single-supply operation, ac cou-
pling offers a convenient way of biasing the analog input signal
to the proper signal range. Figure 25 shows a typical configura-
tion for ac-coupling the analog input signal to the AD9203.
Maintaining the specifications outlined in the data sheet re-
quires careful selection of the component values. The most
important is the f
–3 dB
high-pass corner frequency. It is a func-
tion of R2 and the parallel combination of C1 and C2.
AIN
R1
R2
+
V
BIAS
=
AVDD/2
V
IN
C1
C2
AD9203
Figure 25. AC-Coupled Input
The f
–3 dB
point can be approximated by the equation:
f
–3
dB
= 1/(2
π
×
[
R
2]
C
EQ
)
where
C
EQ
is the parallel combination of C1 and C2. Note that
C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Add a small ceramic or
polystyrene capacitor (on the order of 0.01
μ
F) that is negligibly
inductive at higher frequencies while maintaining a low imped-
ance over a wide frequency range.
There are additional considerations when choosing the resistor
values for an ac-coupled input. The ac-coupling capacitors
integrate the switching transients present at the input of the
AD9203 and cause a net dc bias current, IB, to flow into the
input. The magnitude of the bias current increases as the signal
changes and as the clock frequency increases. This bias current
will result in an offset error of (R1 + R2)
×
IB. If it is necessary
to compensate for this error, consider modifying VBIAS to
account for the resultant offset. In systems that must use dc
coupling, use an op amp to level-shift ground-referenced signals
to comply with the input requirements of the AD9203.
OP AMP SELECTION GUIDE
Op amp selection for the AD9203 is highly application depen-
dent. In general, the performance requirements of any given
application can be characterized by either time domain or fre-
quency domain constraints. In either case, one should carefully
select an op amp that preserves the performance of the A/D.
This task becomes challenging when one considers the AD9203’s
high performance capabilities coupled with other system level
requirements such as power consumption and cost.
The ability to select the optimal op amp may be further compli-
cated by either limited power supply availability and/or limited
acceptable supplies for a desired op amp. Newer, high perfor-
mance op amps typically have input and output range limita-
tions in accordance with their lower supply voltages. As a result,
some op amps will be more appropriate in systems where ac-
coupling is allowed. When dc-coupling is required, op amps’
headroom constraints (such as rail-to-rail op amps) or ones
where larger supplies can be used, should be considered.
The following section describes some op amps currently avail-
able from Analog Devices. Please contact the factory or local
sales office for updates on Analog Devices latest amplifier prod-
uct offerings.
AD8051:
f
–3 dB
= 110 MHz.
Low cost. Best used for driving single-ended ac-coupled con-
figuration. Operates on a 3 V power rail.
AD8052:
Dual Version of above amp.
AD8138
is a higher performance version of AD8131. Its gain is
programmable and provides 14-bit performance.
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