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參數(shù)資料
| 型號： | AD8620BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP JFET 25MHZ DUAL 8SOIC |
| 設(shè)計資源： | Using AD7328 in Appls with Single-Ended Industrial-Level Signals (CN0047) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 60 V/µs |
| 增益帶寬積： | 25MHz |
| 電流 - 輸入偏壓： | 3pA |
| 電壓 - 輸入偏移： | 45µV |
| 電流 - 電源： | 3mA |
| 電流 - 輸出 / 通道： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | ±5 V ~ 13 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8610/AD8620
Rev. F | Page 19 of 24
Input Offset Voltage Adjustment
Offset of AD8610 is very small and normally does not require
additional offset adjustment. However, the offset adjust pins can
be used as shown in Figure 66 to further reduce the dc offset. By
using resistors in the range of 50 kΩ, offset trim range is ±3.3 mV.
R1
V+
VOUT
V–
AD8610
02
73
0-
0
6
7
6
1
5
4
3
2
Figure 66. Offset Voltage Nulling Circuit
Programmable Gain Amplifier (PGA)
The combination of low noise, low input bias current, low input
offset voltage, and low temperature drift make the AD8610/
AD8620 a perfect solution for programmable gain amplifiers.
PGAs are often used immediately after sensors to increase the
dynamic range of the measurement circuit. Historically, the large
on resistance of switches (combined with the large IB currents
of amplifiers) created a large dc offset in PGAs. Recent and
improved monolithic switches and amplifiers completely remove
these problems. A PGA discrete circuit is shown in Figure 67.
In Figure 67, when the 10 pA bias current of the AD8610 is
dropped across the (<5 Ω) RON of the switch, it results in a
negligible offset error.
When high precision resistors are used, as in the circuit of
Figure 67, the error introduced by the PGA is within the
LSB requirement for a 16-bit system.
VIN
VOUT
AD8610
7
4
6
5
1
2
3
IN1
S1
D1
10k
1k
+5V
–5V
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
ADG452
3
2
14
15
11
10
6
7
VL
VDD
13
12
1
16
9
8
74HC139
VSS
4
GND
5
1k
100
11
5pF
G = +1
G = +10
G = +100
G = +1000
+5V
–5V
Y0
Y1
Y2
Y3
G
A
B
A0
A1
02
73
0
-06
7
100
Figure 67. High Precision PGA
1. Room temperature error calculation due to RON and IB
ΔVOS = IB × RON = 2 pA × 5 Ω = 10 pV
Total Offset = AD8610 (Offset) + ΔVOS
Total Offset = AD8610 (Offset_Trimmed) + ΔVOS
Total Offset = 5 μV + 10 pV ≈ 5 μV
2. Full temperature error calculation due to RON and IB
ΔVOS (@ 85°C) = IB (@ 85°C) × RON (@ 85°C) =
250 pA × 15 Ω = 3.75 nV
3. The temperature coefficient of switch and AD8610/AD8620
combined is essentially the same as the TCVOS of the
AD8610/AD8620.
ΔVOS/ΔT(total) = ΔVOS/ΔT(AD8610/AD8620) +
ΔVOS/ΔT(IB × RON)
ΔVOS/ΔT(total) = 0.5 μV/°C + 0.06 nV/°C ≈ 0.5 μV/°C
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