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參數(shù)資料
型號: AD8465WBCPZ-WP
廠商: Analog Devices Inc
文件頁數(shù): 14/16頁
文件大?。?/td> 0K
描述: IC COMPARATOR 1CH LVDS 12LFCSP
標(biāo)準(zhǔn)包裝: 50
類型: 帶鎖銷
元件數(shù): 1
輸出類型: 補充型,LVDS,滿擺幅
電壓 - 電源,單路/雙路(±): 2.5 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 2mV @ 2.5V
電流 - 輸入偏壓(最小值): 5µA @ 2.5V
電流 - 輸出(標(biāo)準(zhǔn)): 50mA
電流 - 靜態(tài)(最大值): 3mA
CMRR, PSRR(標(biāo)準(zhǔn)): 50dB CMRR,60dB PSRR
傳輸延遲(最大): 3ns
磁滯: 100µV
工作溫度: -40°C ~ 125°C
封裝/外殼: 12-VFQFN 裸露焊盤,CSP
安裝類型: 表面貼裝
包裝: 托盤 - 晶粒
產(chǎn)品目錄頁面: 764 (CN2011-ZH PDF)
Data Sheet
AD8465
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
AD8465
VCCO 1
VCCI 2
VEE 3
V
P
4
V
EE
5
V
N
6
9 VEE
8 LE/HYS
7 SDN
12
Q
11
V
E
10
Q
07
95
8-
0
03
NOTES
1. FOR BEST THERMAL PERFORMANCE,
EXPOSED PAD MUST BE SOLDERED
TO THE PCB.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VCCO
Output Section Supply.
2
VCCI
Input Section Supply.
3, 5, 9, 11
VEE
Negative Supply Voltages.
4
VP
Noninverting Analog Input.
6
VN
Inverting Analog Input.
7
SDN
Shutdown. Drive this pin low to shut down the device.
8
LE/HYS
Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, if the comparator is in compare mode.
12
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater
than the analog voltage at the inverting input, VN, if the comparator is in compare mode.
Heat Sink Paddle
VEE
The metallic back surface of the package is electrically connected to VEE. It can be left floating
because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be
soldered to the application board if improved thermal and/or mechanical stability is desired.
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