參數(shù)資料
型號: AD8375ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 4/24頁
文件大?。?/td> 0K
描述: IC AMP VGA DIFF ULDIST 24LFCSP
產(chǎn)品培訓(xùn)模塊: Differential Circuit Design Techniques for Communication Applications
標(biāo)準(zhǔn)包裝: 1
放大器類型: 可變增益
電路數(shù): 1
輸出類型: 差分
轉(zhuǎn)換速率: 5000 V/µs
-3db帶寬: 630MHz
電流 - 輸入偏壓: 900nA
電流 - 電源: 125mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 775 (CN2011-ZH PDF)
其它名稱: AD8375ACPZ-R7DKR
AD8375
Data Sheet
Rev. A | Page 12 of 24
CIRCUIT DESCRIPTION
BASIC STRUCTURE
The AD8375 is a differential variable gain amplifier consisting
of a 150 Ω digitally controlled passive attenuator followed by a
highly linear transconductance amplifier.
06724-
032
gm CORE
AMP
MUX BUFFERS
AD8375
A0 TO A4
DIGITAL
SELECT
ATTENUATOR
VIN+
VCOM
VIN–
VOUT+
VOUT–
Figure 32. Simplified Schematic
Input System
The dc voltage level at the inputs of the AD8375 is set by an
internal voltage reference circuit to about 2 V. This reference is
accessible at VCOM and can be used to source or sink 100 μA.
For cases where a common-mode signal is applied to the inputs,
such as in a single-ended application, an external capacitor
between VCOM and ground is required. The capacitor improves
the linearity performance of the part in this mode. This capacitor
should be sized to provide a reactance of 10 Ω or less at the
lowest frequency of operation. If the applied common-mode
signal is dc, its amplitude should be limited to 0.25 V from
VCOM (VCOM ± 0.25 V).
The device can be powered down by pulling the PWUP pin
down to below 0.8 V. In the powered down mode, the total
current reduces to 3 mA (typical). The dc level at the inputs and
at VCOM remains at about 2 V, regardless of the state of the
PWUP pin.
Output Amplifier
The gain is based on a 150 Ω differential load and varies as RL is
changed per the following equations:
Voltage Gain = 20 × (log(RL/150) + 1)
and
Power Gain = 10 × (log(RL/150) + 2)
The dependency of the gain on the load is due to the open-
collector architecture of the output stage.
The dc current to the outputs of the amplifier is supplied
through two external chokes. The inductance of the chokes and
the resistance of the load determine the low frequency pole of
the amplifier. The parasitic capacitance of the chokes adds to
the output capacitance of the part. This total capacitance in
parallel with the load resistance sets the high frequency pole of
the device. Generally, the larger the inductance of the choke, the
higher its parasitic capacitance. Therefore, the value and type of
the choke should be chosen keeping this trade-off in mind.
For operation frequency of 15 MHz to 700 MHz driving a
150 Ω load, 1 μH chokes with SRF of 160 MHz or higher are
recommended (such as 0805LS-102XJBB from Coilcraft).
The supply current consists of about 50 mA through the VCC
pin and 80 mA through the two chokes combined. The latter
increases with temperature at about 2.5 mA per 10°C.
There are two output pins for each polarity and they are
oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
Gain Control
A 5-bit binary code changes the attenuator setting in 1 dB steps
such that the gain of the device changes from 20 dB (Code 0) to
4 dB (Code 24 and higher).
The noise figure of the device is about 8 dB at maximum gain
setting and it increases as the gain is reduced. The increase in
noise figure is equal to the reduction in gain. The linearity of
the part measured at the output is first-order independent of
the gain setting. From 0 dB to 20 dB gain, OIP3 is approximately
50 dBm into 150 Ω load at 140 MHz (3 dBm per tone). At gain
settings below 0 dB, it drops to approximately 45 dBm.
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