參數(shù)資料
型號(hào)： AD8320-EB
廠(chǎng)商： Analog Devices, Inc.
英文描述： Serial Digital Controlled Variable Gain Line Driver
中文描述： 串行數(shù)字控制可變?cè)鲆婢€(xiàn)路驅(qū)動(dòng)器
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 583K
代理商： AD8320-EB
AD8320
–4–
REV. 0
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8320 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDE RING GUIDE
Model
T emperature Range
Package Description
u
JA
53
°
C/W
Package Option
AD8320ARP
AD8320-EB
–40
°
C to +85
°
C
20-Lead T hermally Enhanced Power SOIC*
Evaluation Board
RP-20
*Shipped in tubes (38 pieces/tube) and dry packed per J-ST D-020.
ABSOLUT E MAX IMUM RAT INGS*
Supply Voltage +V
S
Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +13 V
Input Voltages
Pins 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
3 V
Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5 V
Internal Power Dissipation
Small Outline (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Operating T emperature Range . . . . . . . . . . . –40
°
C to +85
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead T emperature, Soldering 60 seconds . . . . . . . . . . +300
°
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURAT ION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8320
VOUT
VCC
VCC
CLK
DATEN
GND
VCC
PD
VOCM
GND
GND
VIN
VREF
VCC
BYP
GND
GND
SDATA
VCC
GND
PIN FUNCT ION DE SCRIPT IONS
Pin
Function
Description
1
SDAT A
Serial Data Input. T his digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
Clock Input. T he clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0 to 1 transition latches the data bit and a 1 to 0 transfers the data bit to the slave.
T his requires the input serial data word to be valid at or before this clock transition.
Data Enable Low Input. T his port controls the 8-bit parallel data latch and shift register. A Logic 0 to 1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhib-
its serial data transfer into the register. A 1 to 0 transition inhibits the data latch (holds the previous
gain state) and simultaneously enables the register for serial data load.
2
CLK
3
DATEN
4, 11, 12,
13, 15, 16
5
GND
VOCM
Common External Ground Reference.
VCC/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC).
T his port should be externally ac decoupled (0.1
μ
F cap).
Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the
output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and
disables the reverse amplifier.
Common Positive External Supply Voltage.
Output Signal Port. DC biased to approximately VCC/2.
Internal Bypass. T his pin must be externally ac decoupled (0.1
μ
F cap).
Input Reference Voltage (typically 1.9 V at 27
°
C). T his port should be externally ac decoupled
(0.1
μ
F cap).
Analog Voltage Input Signal Port. DC biased to VREF voltage.
6
PD
7, 8, 9, 17, 20 VCC
10
14
18
VOUT
BYP
VREF
19
VIN
WARNNG
ESD SENSITIVE DEVICE
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