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參數(shù)資料
| 型號： | AD8320-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Serial Digital Controlled Variable Gain Line Driver |
| 中文描述： | 串行數(shù)字控制可變增益線路驅(qū)動器 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 583K |
| 代理商： | AD8320-EB |
AD8320
–11–
REV. 0
Basic Connection
Figure 45 shows the basic schematic for operating the AD8320.
Because the amplifier operates from a single supply, the input
signal must be ac-coupled using a 0.1
μ
F capacitor. T he input
pin has a bias level of about 1.9 V. T his bias level is available on
the VREF pin (Pin 18) and can be used to externally bias signals
if dc-coupling is desired. Under all conditions, a 0.1
μ
F decoupling
capacitor must be connected to the VREF pin. If the VREF volt-
age is to be used externally, it should be buffered first.
T he VIN pin of the AD8320 (Pin 19) has an input impedance
of 220
. T ypically, in video applications, 75
termination is
favored. As a result, an external shunt resistance (R1) to ground
of 115
is required to create an overall input impedance of
75
. If 50
termination is required, a 64.9
shunt resistor
should be used. Note, to avoid dc loading of the VIN pin, the
ac-coupling capacitor should be placed between the input pin
and the shunt resistor as shown in Figure 45.
On the output side, the VOUT pin also has a dc bias level. In
this case the bias level is midway between the supply voltage and
ground. T he output signal must therefore be ac-coupled before
being applied to the load. T he dc bias voltage is available on the
VOCM pin (Pin 5) and can be used in dc-coupled applications.
T his node must be decoupled to ground using a 0.1
μ
F capaci-
tor. If the VOCM voltage is to be used externally, it should be
buffered.
Since the AD8320 has a dynamic output impedance of 75
, no
external back termination resistor is required. If the output
signal is being evaluated on 50
test equipment such as a spec-
trum analyzer, a 75
to 50
adapter (commonly called a pad)
should be used to maintain a properly matched circuit.
Varying the Gain
T he gain of the AD8320 can be varied over a range of 36dB,
from –10 dB to +26 dB, by varying the 8-bit gain setting word.
T he timing diagram for AD8320’s serial interface is shown in
Figure 43.
T he write cycle to the device is initiated by the falling edge of
DATEN
. T his is followed by eight clock pulses that clock in the
control word. Because the clock signal is level triggered, data is
effectively clocked on the falling edge of CLK .
After the control word has been clocked in, the
DATEN
line
goes back high, allowing the gain to be updated (this takes
about 30 ns).
T he relationship between gain and control word is given by the
equation:
Gain (V/V)
= 0.077
×
Code
+ 0.316
where
code
is the decimal equivalent of the gain control word
(0 to 255).
T he gain in dB is given by the equation:
Gain
(
dB
) = 20 log
10
(0.077
×
Code
+ 0.316)
T he digital interface also contains an asynchronous power-down
mode. T he normally high
PD
line can be pulled low at any time.
T his turns off the output signal after 45 ns, and reduces the
quiescent current to between 25 mA and 32 mA (depending
upon the power supply voltage). In this mode, the programmed
gain is maintained.
Clock Line Feedthrough
Clock feedthrough results in a 5 mV p-p signal appearing super-
imposed on the output signal (see Figure 32). If this impinges
upon the dynamic range of the application, the clock signal
should be noncontinuous, i.e., should only be turned on for
eight cycles during programming.
Power Supply and Decoupling
T he AD8320 should be powered with a good quality (i.e., low
noise) single supply of between +5 V and +12 V. In order to
achieve an output power level of +18 dBm (6.2 V p-p) into
C6
0.1
m
F
CLK
SDATA
DATEN
PD
DATEN
SDATA
GND GND GND GND GND
POWER-
DOWN
/
SWITCH
INTER.
VOUT
VOCM
C10
0.1
m
F
C8
0.1
m
F
TO DIPLEXER
RIN = 75
V
ATTENUATOR CORE
DATA LATCH
DATA SHIFT REGISTER
CLK
C5
0.1
m
F
C4
0.1
m
F
C7
10
m
F
C2
0.1
m
F
C11
0.1
m
F
VCC
+5V TO +12V
VREF
C12
0.1
m
F
VIN
R1*
115
V
C1
0.1
m
F
INPUT
C3
0.1
m
F
REFERENCE
VCC
VCC
VCC
VCC
GND
BYP
AD8320
*FOR A 75
INPUT
IMPEDANCE
PD
VCC
Figure 45. Basic Connection
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