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參數(shù)資料
| 型號(hào)： | AD8310ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier |
| 中文描述： | LOG OR ANTILOG AMPLIFIER, 440 MHz BAND WIDTH, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 323K |
| 代理商： | AD8310ARM-REEL7 |
AD8310
–9–
REV. A
COMM
ENBL
40k
V
TO BIAS
STAGES
AD8310
Figure 21. ENABLE Interface
Input Interface
Figure 22 shows the essentials of the input interface. C
P
and C
M
are parasitic capacitances; C
D
is the differential input capacitance,
largely due to Q1 and Q2. In most applications both input pins
are ac-coupled. The switches S close when Enable is asserted.
When disabled, bias current I
E
is shut off, and the inputs float;
thus, the coupling capacitors remain charged. If the log amp is
disabled for long periods, small leakage currents will discharge
these capacitors. Then, if they are poorly matched, charging
currents at power-up can generate a transient input voltage that
may block the lower reaches of the dynamic range until it has
become much less than the signal.
TOP-END
DETECTORS
COM
INHI
INLO
C
P
C
D
C
M
COM
4k
V
~3k
V
125
V
6k
V
6k
V
2k
V
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
S
S
VPOS
COMM
I
2.4mA
Q1
Q2
Figure 22. Signal Input Interface
A single-sided signal may be applied via a blocking capacitor to
either Pin 1 or 8, with the other pin ac-coupled to ground. Under
these conditions, the largest input signal that can be handled is
0 dBV (a sine amplitude of 1.4 V) when using a 3 V supply; a
+5 dBV input (2.5 V amplitude) may be handled with a 5 V
supply. When using a fully-balanced drive this maximum input
level is permissible for supply voltages as low as 2.7 V. Above
10 MHz, this is easily achieved using an LC matching network.
Such a network, having an inductor at the input, usefully elimi-
nates the input transient noted above.
Occasionally, it may be desirable to use the dc-coupled potential
of the AD8310, in baseband applications. The main challenge
here is to present the signal at the elevated common-mode input
level, which may require the use of low-noise, low-offset buffer
amplifiers. In some cases, it may be possible to use dual supplies
of
±
3 V, which allows the input pins to operate at ground poten-
tial. The output, which is internally referenced to the COMM
pin (now at –3 V), may be positioned back to ground level, with
essentially no sensitivity to the particular value of the negative
supply.
Offset Interface
The input-referred dc offsets in the signal path are nulled via the
interface associated with Pin 3, shown in Figure 23. Q1 and Q2
are the first-stage input transistors, having slightly unbalanced
load resistors, resulting in a deliberate offset voltage of about
1.5 mV referred to the input pins. Q3 generates a small current
to null this error, dependent on the voltage at the OFLT pin.
When Q1 and Q2 are perfectly matched this voltage is about
1.75 V; in practice, it will range from approximately 1 V to 2.5 V
for an input-referred offset of
±
1.5 mV.
48k
V
125
V
MAIN GAIN
STAGES
Q2
Q1
Q3
16
m
A AT
BALANCE
Q4
g
m
S
AVERAGE
ERROR
CURRENT
OFLT
TO LAST
DETECTOR
C
OFLT
33pF
COMM
VPOS
36k
V
INPUT
STAGE
BIAS, 1.2V
Figure 23. Offset Interface and Offset-Nulling Path
In normal operation using an ac-coupled input signal, the OFLT
pin should be left unconnected. The g
m
cell, which is gated off
when the chip is disabled, converts a residual offset (sensed at a
point near the end of the cascade of amplifiers) to a current.
This is integrated by the on-chip capacitor C
HP
, plus any added
external capacitance C
OFLT
, to generate the voltage that is applied
back to the input stage in the polarity needed to null the output
offset. From a small-signal perspective, this feedback alters the
response of the amplifier, which exhibits a zero in its ac transfer
function, resulting in a closed-loop
high-pass
–3 dB corner at
about 2 MHz. An external capacitor will lower the high-pass
corner to arbitrarily low frequencies; using 1
μ
F, the 3 dB corner
is at 60 Hz.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8310ARMZ | 功能描述:IC LOGARITHMIC AMP 95DB 8-MSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變增益放大器 應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8310ARMZ | 制造商:Analog Devices 功能描述:Operational Amplifier (Op-Amp) IC |
| AD8310ARMZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, Voltage-Out DC-440 MHz, 95 dB Logarithmic Amplifier |
| AD8310ARMZ-REEL7 | 功能描述:IC AMP LOGARITHMIC 8MSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變增益放大器 應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8310ARMZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, Voltage-Out DC-440 MHz, 95 dB Logarithmic Amplifier |
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