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參數(shù)資料
| 型號(hào)： | AD8310 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier |
| 中文描述： | 快速，電壓輸出的DC - 440 MHz的95分貝數(shù)放大器 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 323K |
| 代理商： | AD8310 |
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AD8310
–13–
REV. A
General Matching Procedure
For other center frequencies and source impedances, the following
method can be used to calculate the basic matching parameters.
Step 1: Tune Out C
IN
At a center frequency f
C
, the shunt impedance of the input
capacitance C
IN
can be made to disappear by resonating with a
temporary inductor L
IN
, whose value is given by
L
w C
IN
IN
=
1
when
C
IN
= 1.4 pF. For example, at
f
C
= 100 MHz,
L
IN
= 1.8
μ
H.
Step 2: Calculate C
O
and L
O
Now having a purely resistive input impedance, we can calculate
the nominal coupling elements C
O
and L
O
, using
C
f
R R
L
R R
2
π
f
O
C
M
O
M
C
=
(
)
=
(
)
1
2
π
;
For the AD8310, R
IN
is 1 k
. Thus, if a match to 50
is needed,
at f
C
= 100 MHz, C
O
must be 7.12 pF and L
O
must be 356 nH.
Step 3: Split C
O
Into Two Parts
Since we wish to provide the fully-balanced form of network
shown in Figure 29, two capacitors C1 = C2
each of nominally
twice C
O
, shown as C
M
in the figure, can be used. This requires
a value of 14.24 pF in this example. Under these conditions, the
voltage amplitudes at INHI and INLO will be similar. A some-
what better balance in the two drives may be achieved when C1
is made slightly larger than C2, which also allows a wider range
of choices in selecting from standard values. For example,
capacitors of C1 = 15 pF and C2 = 13 pF may be used (making
C
O
= 6.96 pF).
Step 4: Calculate L
M
The matching inductor required to provide both L
IN
and L
O
is
just the parallel combination of these:
L
M
= L
IN
L
O
/(
L
IN
+
L
O
)
With
L
IN
= 1.8
μ
H and
L
O
= 356 nH, the value of
L
M
to com-
plete this example of a match of 50
at 100 MHz is 297.2 nH.
The nearest standard value of 270 nH may be used with only a
slight loss of matching accuracy. The voltage gain at resonance
depends only on the ratio of impedances, as given by
GAIN
R
R
R
R
IN
S
IN
S
=
=
20
10
log
log
Slope and Intercept Adjustments
Where system (i.e., software) calibration is not available, the
adjustments shown in Figure 31 can be used, either singly or in
combination, to trim the absolute accuracy of the AD8310. The
log slope may be raised or lowered by VR1; the values shown
provide a calibration range of
±
10% (22.6 mV/dB to 27.4 mV/dB),
which includes full allowance for the variability in the value of
the internal resistances. The adjustment may be made by alter-
nately applying two fixed input levels, provided by an accurate
signal generator, spaced over the central portion of the dynamic
range, for example –60 dBV and –20 dBV.
Alternatively, an AM-modulated signal, at about the center of
the dynamic range, may be used. For a modulation depth M,
expressed as a fraction, the decibel range between the peaks and
troughs over one cycle of the modulation period is given by
dB
M
M
=
+
–
20
1
1
10
log
(3)
For example., using a generator output of –40 dBm with a 70%
modulation depth (
M
= 0.7), the decibel range is 15 dB, as the
signal varies from –47.5 dBm to –32.5 dBm.
The log intercept is adjustable by VR2 over a –3 dB range with
the component values shown. VR2 is adjusted while applying an
accurately-known CW signal, preferably near the lower end of the
dynamic range, in order to minimize the effect of any residual
uncertainty in the slope. For example, to position the intercept
to –80 dBm, a test level of –65 dBm may be applied and VR2
adjusted to produce a dc output of 15 dB above zero at 24 mV/dB,
which is 360 mV.
+V
(2.7–5.5V)
0.01
m
F
52.3
V
NC = NO CONNECT
C1
0.01
m
F
NC
INHI ENBL
BFIN VPOS
INLO COMM OFLT VOUT
1
2
AD8310
4.7
V
V
OUT
(RSSI)
SIGNAL
INPUT
10k
V
C2
0.01
m
F
25k
V
VR1
10k
V
R
S
VR2
100k
V
FOR V
POS
= 3V, R
S
= 500k
V
FOR V
POS
= 5V, R
S
= 850k
V
24mV/dB
6
10%
3
4
8
7
6
5
Figure 31. Slope and Intercept Adjustments
Increasing the Slope to a Fixed Value
It is also possible to increase the slope to a new fixed value and
thus increase the change in output for each decibel of input
change. A common example of this is the need to “map” the
output swing of the AD8310 into the input range of an analog-
to-digital converter (ADC) with a rail-to-rail input swing.
Alternatively, a situation might arise, when only a part of the
total dynamic range is required—say, just 20 dB—in an applica-
tion where the nominal input level is more tightly constrained
and a higher sensitivity to a change in this level is required. Of
course, the maximum output will be limited either by the load
resistance and the maximum output current rating of 25 mA, or
by the supply voltage (see Specifications). The slope may easily
be raised by adding a resistor from VOUT to BFIN as shown in
Figure 32. This alters the gain of the output buffer, by means of
stable positive feedback, from its normal value of four to an
effective value which may be as high as sixteen, corresponding
to a slope of 100 mV/dB. The resistor R
SLOPE
is set according
to the equation
R
k
mV dB
Slope
SLOPE
=
9 22
24
1
.
–
/
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