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參數(shù)資料
| 型號(hào)： | AD8310 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier |
| 中文描述： | 快速，電壓輸出的DC - 440 MHz的95分貝數(shù)放大器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 323K |
| 代理商： | AD8310 |
AD8310
–10–
REV. A
0.2pF
BIAS
3k
V
1k
V
4k
V
4k
V
R1
3k
V
2
m
A/dB
0.4pF
1.25k
V
1.25k
V
1.25k
V
1.25k
V
BFIN
0.4pF
60
m
A
VPOS
COMM
BIAS
LGP
LGN
FROM ALL
DETECTORS
VOUT
Figure 24. Simplified Output Interface
Output Interface
The nine detectors generate differential currents, having an
average value that is dependent on the signal input level, plus a
fluctuation at twice the input frequency. These are summed at
nodes LGP and LGN in Figure 24. Further currents are added at
these nodes, to position the intercept, by slightly raising the output
for zero input, and to provide temperature compensation.
For zero-signal conditions, all the detector output currents are
equal. For a finite input, of either polarity, their difference is
converted by the output interface to a single-sided unipolar
current, nominally scaled 2
μ
A/dB (40
μ
A/decade), at the output
pin BFIN. An on-chip resistor, R1, of ~3 k
, converts this
current to a voltage of 6 mV/dB. This is then amplified by a
factor of four in the output buffer, which can drive a current of
up to 25 mA in a grounded load resistor. The overall rise-time
of the AD8310 is under 15 ns; there is also a delay time of about
6 ns when the log amp is driven by an RF burst, starting at zero
amplitude. When driving capacitive loads, it is desirable to add a
low value of load resistor to speed up the return to the baseline;
the buffer is stable for loads of a least 100 pF. The output band-
width may be lowered by adding a grounded capacitor at BFIN.
The time-constant of the resulting single-pole filter is formed
with the 3 k
internal load resistor (having a tolerance of 20%);
thus, to set the –3 dB frequency to 20 kHz, use a capacitor of
2.7 nF. Using 2.7
μ
F, the filter corner is at 20 Hz.
USING THE AD8310
The AD8310 has very high gain and bandwidth. Consequently,
it is susceptible to all signals that appear at the input terminals
within a very broad frequency range. Without the benefit of
filtering, these will be quite indistinguishable from the “wanted”
signal, and will have the effect of raising the apparent noise floor
(that is, lowering the useful dynamic range). For example, while
the signal of interest may be an IF of 50MHz, any of the following
could easily be larger than the IF signal at the lower extremities of
its dynamic range: a few hundred microvolts of 60 Hz hum,
picked up due to poor grounding techniques; spurious coupling
from a digital clock source on the same PC board; local radio
stations; etc. Careful shielding and supply decoupling is therefore
essential. A ground-plane should be used to provide a low-
impedance connection to the common pin COMM, for the
decoupling capacitor(s) used at VPOS, and for the output ground.
Basic Connections
Figure 25 shows the connections needed for most applications.
A supply voltage between 2.7 V and 5.5 V is applied to VPOS
and is decoupled using a 0.01
μ
F capacitor close to the pin.
Optionally, a small series resistor can be placed in the power
line to give additional filtering of power supply noise. The
ENBL input, which has a threshold of approximately 1.3 V (see
Figure 1), should be tied to VPOS when this feature is not needed.
V
(2.7–5.5V)
C2
0.01
m
F
52.3
V
NC = NO CONNECT
C1
0.01
m
F
C4
0.01
m
F
NC
NC
INHI ENBL
BFIN VPOS
INLO COMM OFLT VOUT
AD8310
4.7
OPTIONAL
V
OUT
(RSSI)
SIGNAL
INPUT
Figure 25. Basic Connections
While the AD8310’s input can be driven differentially, the input
signal will, in general, be single-ended. C1 is tied to ground and
the input signal is coupled in through C2. Capacitors C1 and
C2 should have the same value, to minimize start-up transients
when the enable feature is used; otherwise, their values need not
be equal.
The 52.3
resistor combines with the 1.1 k
input impedance
of the AD8310 to yield a simple broadband 50
input match.
An input matching network can also be used (see Input Matching
section).
The coupling time-constant 50
×
C
C
/2, forms a high-pass corner
with a 3 dB attenuation at f
HP
= 1/(
π
×
50
×
C
C
), where C1 =
C2 = C
C
. In high-frequency applications, f
HP
should be as large
as possible, in order to minimize the coupling of unwanted low-
frequency signals. In low-frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This should generally be placed at the gen-
erator side of the coupling capacitors, thus lowering the required
capacitance value for a given high-pass corner frequency.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8310_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, Voltage-Out DC-440 MHz, 95 dB Logarithmic Amplifier |
| AD8310ARM | 功能描述:IC LOGARITHMIC AMP 95DB 8-MSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8310ARM-REEL | 制造商:Analog Devices 功能描述:SP Amp LOG Amp Single R-R I/P 5.5V 8-Pin MSOP T/R |
| AD8310ARM-REEL7 | 功能描述:IC LOGARITHMIC AMP 8-MSOP T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8310ARMZ | 功能描述:IC LOGARITHMIC AMP 95DB 8-MSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
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