參數(shù)資料
型號(hào)： AD8191ASTZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE HDMI/DVI 100-LQFP
標(biāo)準(zhǔn)包裝： 1,000
功能： 開(kāi)關(guān)，DVI/HDMI
電路： 1 x 16:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 帶卷 (TR)
AD8191
Rev. 0 | Page 28 of 32
PCB DIELECTRIC
LAYER 1: SIGNAL (MICROSTRIP)
SILKSCREEN
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
LAYER 3: PWR (REFERENCE PLANE)
LAYER 4: SIGNAL (MICROSTRIP)
W
3W
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
06
12
3-
0
10
Figure 32. Example Board Stackup
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement
of this signal is not critical, but it should be routed as directly
as possible.
When the AD8191 is powered up, one set of the auxiliary in-
puts is passively routed to the outputs. In this state, the AD8191
looks like a 100 Ω resistor between the selected auxiliary inputs
and the corresponding outputs as illustrated in Figure 27. The
AD8191 does not buffer the auxiliary signals, therefore, the
input traces, output traces, and the connection through the
AD8191 all must be considered when designing a PCB to meet
HDMI/DVI specifications. The unselected auxiliary inputs of the
AD8191 are placed into a high impedance mode when the device
is powered up. To ensure that all of the auxiliary inputs of the
AD8191 are in a high impedance mode when the device is powered
off, it is necessary to power the AMUXVCC supply as illustrated
In contrast to the auxiliary signals, the AD8191 buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
Power Supplies
The AD8191 has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are:
AVCC/AVEE
VTTI/AVEE
VTTO/AVEE
DVCC/DVEE
AMUXVCC/DVEE
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8191. The VTTI/AVEE supply (3.3 V)
powers the input termination (see Figure 25). Similarly, the
VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the
maximum allowed voltage on the auxiliary lines. For example,
if the DDC bus is using 5 V I2C, then AMUXVCC should be
connected to +5 V relative to DVEE.
In a typical application, all pins labeled AVEE or DVEE should
be connected directly to ground. All pins labeled AVCC,
DVCC, VTTI, or VTTO should be connected to 3.3 V, and
Pin AMUXVCC tied to 5 V. The supplies can also be powered
individually, but care must be taken to ensure that each stage of
the AD8191 is powered correctly.
Power Supply Bypassing
The AD8191 requires minimal supply bypassing. When
powering the supplies individually, place a 0.01 μF capacitor
between each 3.3 V supply pin (AVCC, DVCC, VTTI, and
VTTO) and ground to filter out supply noise. Generally, bypass
capacitors should be placed near the power pins and should
connect directly to the relevant supplies (without long inter-
vening traces). For example, to improve the parasitic inductance
of the power supply decoupling capacitors, minimize the trace
length between capacitor landing pads and the vias as shown in
EXTRA ADDED INDUCTANCE
RECOMMENDED
NOT RECOMMENDED
0
6123-
033
Figure 33. Recommended Pad Outline for Bypass Capacitors
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