參數(shù)資料
型號(hào): AD8191AASTZ
廠商: Analog Devices Inc
文件頁數(shù): 6/28頁
文件大?。?/td> 0K
描述: IC HDMI/DVI SWITCH 4:1 100LQFP
標(biāo)準(zhǔn)包裝: 1
功能: 開關(guān),DVI/HDMI
電路: 1 x 16:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
AD8191A
Rev. 0 | Page 14 of 28
The AD8191A requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8191A are
enabled by programming the TX_PTO bit of the transmitter
settings register or by setting the PP_OTO pin of the parallel
control interface. The internal terminations of the AD8191A
default to the setting indicated by PP_OTO upon reset. External
terminations can be provided either by on-board resistors or by
the input termination resistors of an HDMI/DVI receiver. If
both the internal terminations are enabled and external termi-
nations are present, set the output current level to 20 mA by
programming the TX_OCL bit of the transmitter settings
register through the serial control interface or by setting the
PP_OCL pin of the parallel control interface. The output
current level defaults to the level indicated by PP_OCL upon
reset. If only external terminations are provided (if the internal
terminations are disabled), set the output current level to 10 mA
by programming the TX_OCL bit of the transmitter settings
register or by setting the PP_OCL pin of the parallel control
interface. The high speed outputs must be disabled if there are
no output termination resistors present in the system.
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register through the serial control interface,
or by setting the PP_PE bus of the parallel control interface. No
specific cable length is suggested for a particular pre-emphasis
setting because cable performance varies widely between
manufacturers.
AUXILIARY SWITCH
The auxiliary (low speed) lines have no amplification. They are
routed using a passive switch that is bandwidth compatible with
the standard speed I2C. The schematic equivalent for this
passive connection is shown in Figure 27.
AUX_COM0
AUX_A0
CAUX
RAUX
07
01
3-
02
7
Figure 27. Auxiliary Channel Simplified Schematic,
AUX_A0 to AUX_COM0 Routing Example
When turning off the AD8191A, care needs to be taken with the
AMUXVCC supply to ensure that the auxiliary multiplexer pins
remain in a high impedance state. A scenario that illustrates this
requirement is one where the auxiliary multiplexer is used to
switch the display data channel (DDC) bus. In some applications,
additional devices can be connected to the DDC bus (such as an
EEPROM with EDID information) upstream of the AD8191A.
Extended display identification data (EDID) is a VESA standard-
defined data format for conveying display configuration
information to sources to optimize display use. EDID devices
may need to be available via the DDC bus, regardless of the
state of the AD8191A and any downstream circuit. For this
configuration, the auxiliary inputs of the powered down
AD8191A need to be in a high impedance state to avoid
pulling down on the DDC lines and preventing these other
devices from using the bus.
The AD8191A requires 5 V on its supply pin, AMUXVCC, in
order for the AUXMUX channels to be high impedance. When
a TV is turned off, it cannot provide such a supply; however, it
can be provided from any HDMI source that is plugged into it.
A Schottky diode network, as shown in Figure 28, uses the 5 V
supply (Pin 18) from any HDMI/DVI source to power AMUXVCC
and guarantee high impedance of the auxiliary multiplexer pins.
The AMUXVCC supply does not draw any significant static
current. The use of diodes ensures that connected HDMI sources
do not load this circuit if their 5 V pin is low impedance when
turned off. The 100 kΩ resistor ensures that a minimum of
current flows through the diodes to keep them forward biased.
This precaution does not need to be taken if the DDC peripheral
circuitry is connected to the bus downstream of the AD8191A.
PERIPHERAL
CIRCUITRY
PERIPHERAL
CIRCUITRY
+5V SOURCE C
+5V SOURCE D
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
I<50mA
PERIPHERAL
CIRCUITRY
PERIPHERAL
CIRCUITRY
SOURCE A +5V
SOURCE B +5V
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
I<50mA
AMUXVCC
AD8191A
+5V INTERNAL
(IF ANY)
07
01
3-
02
8
BAT54L
100k
Figure 28. Suggested AMUXVCC Power Scheme
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