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參數(shù)資料
| 型號： | AD8138AAR-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD8138AAR |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 差分 |
| 板類型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 8-SOIC 封裝 |
AD8138
Rev. F | Page 21 of 24
HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 46 shows a simplified front-end
connection for an AD8138 driving an AD9224, a 12-bit,
40 MSPS ADC. The ADC works best when driven differentially,
which minimizes its distortion. The AD8138 eliminates the
need for a transformer to drive the ADC and performs single-
ended-to-differential conversion, common-mode level-shifting,
and buffering of the driving signal.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of
49.9 Ω resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it
runs from supplies of ±5 V.
The AD8138 is configured with unity gain for a single-ended,
input-to-differential output. The additional 23 Ω, 523 Ω total, at
the input to IN is to balance the parallel impedance of the
50 Ω source and its 50 Ω termination that drives the
noninverting input.
The signal generator has a ground-referenced, bipolar output,
that is, it drives symmetrically above and below ground.
common-mode of the AD8138 at 2.5 V, which is the midsupply
level for the AD9224. This voltage is bypassed by a 0.1 μF
capacitor.
The full-scale analog input range of the AD9224 is set to
4 V p-p, by shorting the SENSE terminal to AVSS. This has
been determined to be the scaling to provide minimum
harmonic distortion.
For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180° out of phase. With a
common-mode voltage at the output of 2.5 V, each AD8138
output swings between 1.5 V and 3.5 V.
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used to
test the circuit in Figure 46. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the spurious-free
dynamic range (SFDR) was measured at 85 dBc.
49.9
0.1pF
523
499
49.9
499
VINB
+5V
DRVDD
AVDD
VINA
+5V
AD9224
VOCM
AD8138
–5V
SENSE
+
DIGITAL
OUTPUTS
0.1pF
DRVSS
CML
AVSS
49.9
50
SOURCE
8
2
1
6
3
5
4
24
23
15 26
16 25
28
17
22
27
01
07
3-
0
45
Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC
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