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| 型號： | AD8137YRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP DIFF R-R LP 20MA 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分，滿擺幅 |
| 轉(zhuǎn)換速率： | 450 V/µs |
| -3db帶寬： | 110MHz |
| 電流 - 輸入偏壓： | 500nA |
| 電壓 - 輸入偏移： | 700µV |
| 電流 - 電源： | 3.2mA |
| 電流 - 輸出 / 通道： | 20mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 12 V，± 2.7 V ~ 6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
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AD8137
Data Sheet
Rev. E | Page 26 of 32
Estimating DC Errors
Primary differential output offset errors in the AD8137 are due
to three major components: the input offset voltage, the offset
between the VAN and VAP input currents interacting with the
feedback network resistances, and the offset produced by the
dc voltage difference between the input and output common-
mode voltages in conjunction with matching errors in the
feedback network.
The first output error component is calculated as
+
=
G
F
IO
R
V
Vo_e1
, or equivalently as VIO/β
(21)
where VIO is the input offset voltage.
The second error is calculated as
( )
F
IO
G
F
G
F
IO
R
I
R
I
Vo_e
=
+
+
=
2
(22)
where IIO is defined as the offset between the two input bias
currents.
The third error voltage is calculated as
Vo_e3 = Δenr × (VICM VOCM)
(23)
where Δenr is the fractional mismatch between the two feedback
resistors.
The total differential offset error is the sum of these three error
sources.
Additional Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network still forces the
output voltages to remain balanced, even when the RF/RG feed-
back networks are mismatched. The mismatch, however, causes
a gain error proportional to the feedback network mismatch.
Ratio-matching errors in the external resistors degrade the
ability to reject common-mode signals at the VAN and VIN input
terminals, similar to a four resistor, difference amplifier made
from a conventional op amp. Ratio-matching errors also produce a
differential output component that is equal to the VOCM input
voltage times the difference between the feedback factors (βs).
In most applications using 1% resistors, this component amounts
to a differential dc offset at the output that is small enough to
be ignored.
Driving a Capacitive Load
A purely capacitive load reacts with the bondwire and pin
inductance of the AD8137, resulting in high frequency ringing
in the transient response and loss of phase margin. One way to
minimize this effect is to place a small resistor in series with
each output to buffer the load capacitance. The resistor and load
capacitance forms a first-order, low-pass filter; therefore, the
resistor value should be as small as possible. In some cases, the
ADCs require small series resistors to be added on their inputs.
Figure 37 and Figure 40 illustrate transient response vs. capacitive
load and were generated using series resistors in each output
and a differential capacitive load.
Layout Considerations
Standard high speed PCB layout practices should be adhered
to when designing with the AD8137. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply pins.
To minimize stray capacitance at the summing nodes, the
copper in all layers under all traces and pads that connect to
the summing nodes should be removed. Small amounts of stray
summing-node capacitance cause peaking in the frequency
response, and large amounts can cause instability. If some stray
summing-node capacitance is unavoidable, its effects can be
compensated for by placing small capacitors across the feedback
resistors.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most high
speed signal applications, and they require at least one line
termination. In analog applications, a matched resistive termination
is generally placed at the load end of the line. This section deals
with how to properly terminate a single-ended input to the AD8137.
The input resistance presented by the AD8137 input circuitry
is seen in parallel with the termination resistor, and its loading
effect must be taken into account. The Thevenin equivalent
circuit of the driver, its source resistance, and the termination
resistance must all be included in the calculation as well. An
exact solution to the problem requires solution of several
simultaneous algebraic equations and is beyond the scope of
this data sheet. An iterative solution is also possible and is easier,
especially considering the fact that standard resistor values are
generally used.
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