參數(shù)資料
型號： AD8110ASTZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/29頁
文件大小： 0K
描述： IC VIDEO CROSSPOINT SWIT 80LQFP
標準包裝： 1
功能： 視頻交叉點開關(guān)
電路： 1 x 16:8
電壓電源： 雙電源
電壓 - 電源，單路/雙路(±)： ±4.5 V ~ 5.5 V
電流 - 電源： 38mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應商設(shè)備封裝： 80-LQFP（12x12）
包裝： 托盤
REV. A
AD8110/AD8111
–7–
PIN FUNCTION DESCRIPTIONS
Pin Name
Pin Numbers
Pin Description
INxx
66, 68, 70, 72, 74, 76, 78,
Analog Inputs; xx = Channel Numbers 00 Through 15.
1, 3, 5, 7, 9, 11, 13, 15, 64
DATA IN
57
Serial Data Input, TTL Compatible.
CLK
58
Clock, TTL Compatible. Falling Edge Triggered.
DATA OUT
59
Serial Data Out, TTL Compatible.
UPDATE
56
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “High.”
RESET
61
Disable Outputs, Active “Low.”
CE
60
Chip Enable, Enable “Low.” Must be “l(fā)ow” to clock in and latch data.
SER/PAR
55
Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.
OUTyy
41, 38, 35, 32, 29, 26, 23, 20
Analog Outputs yy = Channel Numbers 00 Through 07.
AGND
2, 4, 6, 8, 10, 12, 14, 16, 46
Analog Ground for Inputs and Switch Matrix.
65, 67, 69, 71, 73, 75, 77
DVCC
63, 79
5 V for Digital Circuitry.
DGND
62, 80
Ground for Digital Circuitry.
AVEE
17, 45
–5 V for Inputs and Switch Matrix.
AVCC
18, 44
+5 V for Inputs and Switch Matrix.
AGNDxx
42, 39, 36, 33, 30, 27, 24, 21
Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected.
AVCCxx/yy
43, 37, 31, 25, 22, 19
+5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
AVEExx/yy
40, 34, 28, 22
–5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
A0
54
Parallel Data Input, TTL Compatible (Output Select LSB).
A1
53
Parallel Data Input, TTL Compatible (Output Select).
A2
52
Parallel Data Input, TTL Compatible (Output Select MSB).
D0
51
Parallel Data Input, TTL Compatible (Input Select LSB).
D1
50
Parallel Data Input, TTL Compatible (Input Select).
D2
49
Parallel Data Input, TTL Compatible (Input Select).
D3
48
Parallel Data Input, TTL Compatible (Input Select MSB).
D4
47
Parallel Data Input, TTL Compatible (Output Enable).
ESD
INPUT
VCC
AVEE
ESD
OUTPUT
VCC
AVEE
1k
(AD8111 ONLY)
ESD
RESET
VCC
20k
DGND
ESD
INPUT
VCC
DGND
ESD
OUTPUT
VCC
2k
DGND
Figure 5. I/O Schematics
a. Analog Input
b. Analog Output
c.
Reset Input
d. Logic Input
e. Logic Output
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