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| 型號： | AD8105ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 304BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 32:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 電流 - 電源： | 340mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 304-BGA（31x31） |
| 包裝： | 托盤 |
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AD8104/AD8105
Rev. 0 | Page 29 of 36
Differential Gain
The specified signal path gain of the AD8104/AD8105 refers to
its differential gain. For the AD8104, the gain of +1 means that
the difference in voltage between the two output terminals is
equal to the difference applied between the two input terminals.
For the AD8105, the ratio of output difference voltage to
applied input difference voltage is +2.
The common mode, or average voltage of the pair of output
signals is set by the voltage on the VOCM pin. This voltage is
typically set to midsupply (often ground), but can be moved
approximately ±0.5 V to accommodate cases where the desired
output common-mode voltage may not be midsupply (as in the
case of unequal split supplies). Adjusting VOCM can limit
differential swing internally below the specifications listed in
Regardless of the differential gain of the device, the common-
mode gain for the AD8104 and AD8105 is +1 to the output.
This means that the common mode of the output voltages
directly follows the reference voltage applied to the VOCM input.
The VOCM reference is a high speed signal input, common to
all output stages on the device. It requires only small amounts of
bias current, but noise appearing on this pin is buffered to the
outputs of all the output stages. As such, the VOCM node should
be connected to a low noise, low impedance voltage to avoid
being a source of noise, offset, and crosstalk in the signal path.
Termination
The AD8104/AD8105 are designed to drive 150 Ω on each
output (or an effective 300 Ω differential), but the output stage
is capable of supplying the current to drive 100 Ω loads (200 Ω
differential) over the specified operating temperature range. If
care is taken to observe the maximum power derating curves,
the output stage can drive 75 Ω loads with slightly reduced slew
rate and bandwidth (an effective 150 Ω differential load).
Termination at the load end is recommended for best signal
integrity. This load termination is often a resistor to a ground
reference on each individual output. By terminating to the
same voltage level that drives the VOCM reference, the power
dissipation due to dc termination current is reduced. In
differential signal paths, it is often desirable to terminate
differentially, with a single resistor across the differential
outputs at the load end. This is acceptable for the AD8104/
AD8105, but when the device outputs are placed in a disabled
state, a small amount of dc bias current is required if the output
is to present as a high impedance over an excursion of output
bus voltages. If the AD8104/AD8105 disabled outputs are
floated (or simply tied together by a resistor), internal nodes
saturate and an increase in disabled output current may
be observed.
For best pulse response, it is often desirable to place a series
resistor in each output to match the characteristic impedance
and termination of the output trace or cable. This is known as
back-termination, and helps shorten settling time by terminating
reflected signals when driving a load that is not accurately
terminated at the load end. A side effect of back-termination is
an attenuation of the output signal by a factor of two. In this
case, a gain of two is usually necessary somewhere in the signal
path to restore the signal.
OPn
ONn
50
100
+
–
AD8104/
AD8105
06
61
2-
06
8
Figure 68. Example of Back-Terminated Differential Load
Single-Ended Output
Usage
The AD8104/AD8105 output pairs can be used single-endedly,
taking only one output and not using the second. This is often
desired to reduce the routing complexity in the design, or
because a single-ended load is being driven directly. This mode
of operation produces good results, but has some shortcomings
when compared to taking the output differentially. When
observing the single-ended output, noise that is common to
both outputs appears in the output signal. This includes thermal
noise in the chip biasing, as well as crosstalk that is coupled into
the signal path. This component noise and crosstalk is equal in
both outputs, and as such can be ignored by a differential
receiver with a high common-mode rejection ratio. However,
when taking the output single-ended, this noise is present with
respect to the ground (or VOCM) reference and is not rejected.
When observing the output single-ended, the distribution of
offset voltages appears greater. In the differential case, the
difference between the outputs when the difference between the
inputs is zero is a small differential offset. This offset is created
from mismatches in components of the signal path, which must
be corrected by the finite differential loop gain of the device. In
the single-ended case, this differential offset is still observed,
but an additional offset component is also relevant. This
additional component is the common-mode offset, which is a
difference between the average of the outputs and the VOCM
reference. This offset is created by mismatches that affect the
signal path in a common-mode manner, and is corrected by the
finite common-mode loop gain of the device. A differential
receiver would reject this common-mode offset voltage, but in
the single-ended case, this offset is observed with respect to the
signal ground. The single-ended output sums half the differen-
tial offset voltage and all of the common-mode offset voltage for
a net increase in observed offset.
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