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| 型號： | AD8105ABPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 32X16 304BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 32:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.5V |
| 電流 - 電源： | 340mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 304-BGA（31x31） |
| 包裝： | 托盤 |
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600 MHz, 32 × 16 Buffered
Analog Crosspoint Switch
AD8104/AD8105
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
FEATURES
High channel count, 32 × 16 high speed, nonblocking
switch array
Differential or single-ended operation
Differential G = +1 (AD8104) or G = +2 (AD8105)
Flexible power supplies
Single +5 V supply, or dual ±2.5 V supplies
Serial or parallel programming of switch array
High impedance output disable allows connection of
multiple devices with minimal loading on output bus
Excellent video performance
>50 MHz 0.1 dB gain flatness
0.05% differential gain error (RL = 150 Ω)
0.05° phase error (RL = 150 Ω)
Excellent ac performance
Bandwidth: 600 MHz
Slew rate: 1800 V/μs
Settling time: 2.5 ns to 1%
Low power of
1.7 W
Low all hostile crosstalk
< 70 dB @ 5 MHz
< 40 dB @ 600 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
304-ball BGA package (31 mm × 31 mm)
APPLICATIONS
Routing of high speed signals including
RGB and component video routing
KVM
Compressed video (MPEG, wavelet)
Data communications
FUNCTIONAL BLOCK DIAGRAM
2
INPUT
RECEIVER
G = +1*
G = +2**
OUTPUT
BUFFER
G = +1
16
512
S
E
T
I
N
DI
V
IDUA
L
,O
R
E
S
E
T
A
LL
O
U
TP
U
TS
T
O
FF
E
N
A
B
LE
/D
IS
A
B
LE
96
VPOS
VNEG
VOCM
32
I
N
PUT
PAI
R
S
RESET
UPDATE
CLK
DATA IN
WE
SER/PAR
DATA
OUT
16
O
U
T
P
UT
P
A
IR
S
SWITCH
MATRIX
96
D0 D1 D2 D3 D4 D5
VDD
DGND
A0
A1
A2
A3
AD8104/
AD8105
1
0
192-BIT SHIFT REGISTER
WITH 6-BIT
PARALLEL LOADING
PARALLEL LATCH
DECODE
16 × 6:32 DECODERS
*AD8104 ONLY
**AD8105 ONLY
0
6
612-
001
96
NO
CONNECT
Figure 1.
GENERAL DESCRIPTION
The AD8104/AD8105 are high speed, 32 × 16 analog crosspoint
switch matrices. They offer 600 MHz bandwidth and slew rate of
1800 V/μs for high resolution computer graphics (RGB) signal
switching. With less than 70 dB of crosstalk and 90 dB isola-
tion (@ 5 MHz), the AD8104/AD8105 are useful in many high
speed applications. The 0.1 dB flatness, which is greater than
50 MHz, makes the AD8104/AD8105 ideal for composite video
switching.
The AD8104/AD8105 include 16 independent output buffers
that can be placed into a high impedance state for paralleling
crosspoint outputs so that off-channels present minimal loading
to an output bus. The AD8104 has a differential gain of +1,
while the AD8105 has a differential gain of +2 for ease of use
in back-terminated load applications. They operate as fully
differential devices or can be configured for single-ended
operation. Either a single +5 V supply or dual ±2.5 V supplies
can be used, while consuming only 340 mA of idle current with
all outputs enabled. The channel switching is performed via a
double-buffered, serial digital control (which can accommodate
daisy-chaining of several devices), or via a parallel control,
allowing updating of an individual output without reprogram-
ming the entire array.
The AD8104/AD8105 are packaged in a 304-ball BGA package
and are available over the extended industrial temperature
range of 40°C to +85°C.
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