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參數(shù)資料
| 型號： | AD808-622BRRL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Ic = 500 mA; Package: PG-SOT223-4; Polarity: NPN; V<sub>CEO</sub> (max): 60.0 V; P<sub>tot</sub> (max): 2,000.0 mW; h<sub>FE</sub> (min): 100.0 - 250.0; I<sub>C</sub>: 1,000.0 mA; |
| 中文描述： | RECEIVER, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | AD808-622BRRL7 |
AD808
REV. 0
–9–
USING T HE AD808
Acquisition T ime
T his is the transient time, measured in bit periods, that required
for the AD808 to lock onto the input data from its free running
state.
Ground Planes
T he use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
T he use of a 10
μ
F capacitor between V
CC
and ground is recom-
mended. T he +5 V power supply connection to V
CC2
should be
carefully isolated. T he V
CC2
pin is used inside the AD808 to
provide the CLK OUT and DAT AOUT signals.
Use a 0.1
μ
F decoupling capacitor between IC power supply
input and ground. T his decoupling capacitor should be posi-
tioned as closed to the IC as possible. Refer to the schematic in
Figure 15 for advised connections.
T ransmission Lines
Use 50
transmission line for PIN, NIN, CLK OUT , and
DAT AOUT signals.
T erminations
Use metal, thick-film, 1% termination resistors for PIN, NIN,
CLK OUT , and DAT AOUT signals. T hese termination resistors
must be positioned as close to the IC as possible.
Use individual connections, not daisy chained, for connections
from the +5 V to load resistors for PIN, NIN, CLK OUT , and
DAT AOUT signals.
Loop Damping Capacitor, C
D
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.47
μ
F,
±
20% capacitor provides < 0.1 dB jitter
peaking.
AD808 Output Squelch Circuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (V
CC2
, Pin 3) to squelch clock and
data outputs when SDOUT indicates a loss of signal (Figure
16). T he V
supply pin draws roughly 72 mA (14 mA for each
of 4 ECL loads, plus 16 mA for all 4 ECL output stages). T his
means that selection of a FET with ON RESIST ANCE of
0.5
will affect the common mode of the ECL outputs by
only 36 mV.
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
V
EE
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
EE
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
V
CC2
AD808
TO V
CC1
, AV
CC
, AV
CC2
P_FET
BYPASS
CAP
5V
Figure 16. Squelch Circuit Schematic
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