參數資料
型號： AD808-622BRRL7
廠商： ANALOG DEVICES INC
元件分類： 數字傳輸電路
英文描述： Ic = 500 mA; Package: PG-SOT223-4; Polarity: NPN; V<sub>CEO</sub> (max): 60.0 V; P<sub>tot</sub> (max): 2,000.0 mW; h<sub>FE</sub> (min): 100.0 - 250.0; I<sub>C</sub>: 1,000.0 mA;
中文描述： RECEIVER, PDSO16
封裝： 0.150 INCH, SOIC-16
文件頁數： 8/12頁
文件大?。?/td> 145K
代理商： AD808-622BRRL7
REV. 0
–8–
AD808
1
2
5
6
7
3
4
8
V
EE
SDOUT
NIN
AV
CC1
THRADJ
AV
EE
AD808
PIN
16
15
12
11
10
14
13
9
R10
154
V
R9
154
V
R6 100
V
C7
R5 100
V
R1
100
V
R2
100
V
C1 0.1
m
F
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
C5 0.1
m
F
C2
0.1
m
F
R4
100
V
R8 100
V
R7 100
V
R3
100
V
C8
R12
154
V
TP1
TP2
R11
154
V
CD
TP7
SDOUT
TP5
TP6
R
THRESH
C11
10
m
F
C10
GND
R14
49.9
V
R15
49.9
V
C12
0.1
m
F
C4 0.1
m
F
C3 0.1
m
F
C6
0.1
m
F
J1
J2
J3
J4
+5V
TP3
TP4
NOTE: INTERCONNECT RUN
UNDER DUT
VECTOR PINS SPACED FOR RN55C
VECTOR PINS SPACED THROUGH-HOLE
CAPACITOR ON VECTOR CUPS; COMPONENT
SHOWN FOR REFERENCE ONLY
TP8
J5
C9
R13
301
V
R16 3.65k
V
J6
J7
C13 0.1
m
F
C14 0.1
m
F
PIN
NIN
50
STRIP LINE
EQUAL LENGTH
NOTE:
C7–C10 ARE 0.1μF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPxoTEST POINTS ARE VECTORBOARD K24A/M PINS
DATAOUTN
DATAOUTP
V
CC2
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
AV
CC2
Figure 15. Evaluation Board Schematic
Center Frequency Clamp (Figure 13)
An N-channel FET circuit can be used to bring the AD808
VCO center frequency to within
±
10% of 622 MHz when
SDOUT indicates a Loss of Signal (LOS). T his effectively re-
duces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. T he N-FET can have “on” resistance as high
as 1 k
and still attain effective clamping. However, the chosen
N-FET should have greater than 10 M
“off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
V
EE
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
EE
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
V
CC2
AD808
N_FET
C
D
Figure 13. Center Frequency Clamp Schematic
RBW:
30Hz ST: 3.07 min RANGE: R=
0, T=
0dBm
DIV
20.00m
C
D
0.047
0.10
PEAK
0.11
0.07
0.04
DIV
36.00m
START
STOP
500.000Hz
100 000.000Hz
Figure14. J itter Transfer vs. C
D
相關PDF資料
PDF描述
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