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參數(shù)資料

型號：	AD7998BRUZ-1REEL3
廠商：	Analog Devices, Inc.
英文描述：	8-Channel, 10- and 12-Bit ADCs with I2CCompatible
中文描述：	8通道，10 -和12位ADC與I2CCompatible
文件頁數(shù)：	21/32頁
文件大?。?/td>	1056K
代理商：	AD7998BRUZ-1REEL3

AD7997/AD7998

Hysteresis Register (CH1/CH2/CH3/CH4)

Each hysteresis register is a 16-bit read/write register, of which

only the 12 LSBs are used. The hysteresis register stores the

hysteresis value,

when using the limit registers. Each pair of

limit registers has a dedicated hysteresis register. The hysteresis

value determines the reset point for the ALERT pin/Alert_Flag

if a violation of the limits has occurred. For example, if a

hysteresis value of 8 LSBs is required on the upper and lower

limits of Channel 1, the 12-bit word, 0000 0000 0000 1000,

should be written to the hysteresis register of CH1, the address

of which is shown in Table 8. On power-up, the hysteresis

registers contain a value of 2 for the AD7997 and a value of 8

for the AD7998. If a different hysteresis value is required, that

value must be written to the hysteresis register for the channel

in question. For the AD7997, D1 and D0 of the hysteresis

Table 19. Hysteresis Register (First Read/Write)

D15

D14

D13

D12

Table 20. Hysteresis Register (Second Read/Write)

Using the Limit Registers to Store Min/Max Conversion

Results for CH1 to CH4

If full scale, that is, all 1s, is written to the hysteresis register for

a particular channel, the DATA

HIGH

and DATA

LOW

registers for

that channel no longer act as limit registers as previously

described, but instead act as storage registers for the maximum

and minimum conversion results returned from conversions on

a channel over any given period of time. This function is useful

in applications where the widest span of actual conversion

results is required rather than using the ALERT to signal that an

intervention is necessary. This function could be useful for

monitoring temperature extremes during refrigerated goods

transportation. It must be noted that on power-up, the contents

of the DATA

HIGH

contents of the DATA

LOW

registers are zero scale by default.

Therefore, minimum and maximum conversion values being

stored in this way are lost if power is removed or cycled.

Rev. 0 | Page 21 of 32

D11

B11

D10

B10

ALERT STATUS REGISTER (CH1 TO CH4)

The alert status register is an 8-bit, read/write register that

provides information on an alert event. If a conversion result

activates the ALERT pin or the Alert_Flag bit in the conversion

result register, as described in the Limit Registers section, the

alert status register may be read to gain further information.

The Alert Status Register contains two status bits per channel,

one corresponding to the DATA

HIGH

limit and the other to the

DATA

LOW

limit. The bit with a status of 1 shows where the

violation occurred—that is, on which channel—and whether

the violation occurred on the upper or lower limit. If a second

alert event occurs on the other channel between receiving the

first alert and interrogating the alert status register, the

corresponding bit for that alert event is also set.

The alert status register only contains information for CH1 to

CH4 because these are the only channels with associated limit

registers.

The entire contents of the alert status register can be cleared by

writing 1,1, to Bits D2 and D1 in the configuration register, as

shown in Table 12. This may also be done by writing all 1s to

the alert status register itself. Thus, if the alert status register is

addressed for a write operation, which is all 1s, the contents of

the alert status register are cleared or reset to all 0s.

Table 21. Alert Status Register

CH4

CH3

CH2

Table 22. Alert Status Register Bit Function Description

Bit

Mnemonic

If bit is set to 1, violation of…

CH1

DATA

LOW

limit on Channel 1.