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參數(shù)資料
| 型號(hào)： | AD7991YRJZ-1RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 4CH I2C SOT23-8 |
| 產(chǎn)品變化通告： | AD7991,5,9 Offset Error Change 17/Sept/2010 |
| 設(shè)計(jì)資源： | Using AD8599 as an Ultralow Distortion Driver for the AD7991 (CN0043) |
| 標(biāo)準(zhǔn)包裝： | 10,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 4.68mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極 |
| 配用： | EVAL-AD7991EBZ-ND - BOARD EVAL FOR AD7991 |
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AD7991/AD7995/AD7999
Rev. B | Page 5 of 28
The temperature range for the Y version is 40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, VREF = 2.5 V, fSCL = 3.4 MHz,
and TA = TMIN to TMAX.
Table 3.
A Version2
Y Version
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions/Comments
See the
section, fIN = 10 kHz sine wave for fSCL from
1.7 MHz to 3.4 MHz
fIN = 1 kHz sine wave for fSCL up to 400 kHz
Signal-to-Noise and
Distortion (SINAD)5
61.5
61
dB
Total Harmonic Distortion
85
75
dB
Peak Harmonic or Spurious
Noise (SFDR)5
85
76
dB
Intermodulation
Distortion (IMD)5
fa = 11 kHz, fb = 9 kHz for fSCL from 1.7 MHz to
3.4 MHz
fa = 5.4 kHz, fb = 4.6 kHz for fSCL up to 400 kHz
Second-Order Terms
90
dB
Third-Order Terms
86
dB
Channel-to-Channel
90
dB
fIN = 10 kHz
Full-Power Bandwidth5
14
MHz
@ 3 dB
1.5
MHz
@ 0.1 dB
DC ACCURACY3, 6
Resolution
10
Bits
Integral Nonlinearity5
±0.4
LSB
Differential Nonlinearity5
±0.4
LSB
Offset Error5
±1
±2.25
LSB
Guaranteed no missed codes to 10 bits
Offset Error Matching
±0.04
±0.2
LSB
Offset Temperature Drift
4.13
ppm/°C
Gain Error5
±0.15
±0.5
LSB
Gain Error Matching
±0.06
±0.25
LSB
Gain Temperature Drift
0.50
ppm/°C
ANALOG INPUT
Input Voltage Range
0
VREF
0
VREF
V
VREF = VIN3/VREF or VDD
DC Leakage Current
±1
μA
Input Capacitance
34
pF
Channel 0 to Channel 2—during acquisition
phase
4
pF
Channel 0 to Channel 2—outside acquisition
phase
35
pF
Channel 3—during acquisition phase
5
pF
Channel 3—outside acquisition phase
REFERENCE INPUT
VREF Input Voltage Range
1.2
VDD
1.2
VDD
V
DC Leakage Current
±1
μA
VREF Input Capacitance
5
pF
Outside conversion phase
35
pF
During conversion phase
Input Impedance
69
kΩ
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