參數(shù)資料
型號： AD7991YRJZ-1RL
廠商： Analog Devices Inc
文件頁數(shù)： 17/28頁
文件大小： 0K
描述： IC ADC 12BIT 4CH I2C SOT23-8
產(chǎn)品變化通告： AD7991,5,9 Offset Error Change 17/Sept/2010
設(shè)計(jì)資源： Using AD8599 as an Ultralow Distortion Driver for the AD7991 (CN0043)
標(biāo)準(zhǔn)包裝： 10,000
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 4.68mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-8
供應(yīng)商設(shè)備封裝： SOT-23-8
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極
配用： EVAL-AD7991EBZ-ND - BOARD EVAL FOR AD7991
AD7991/AD7995/AD7999
Rev. B | Page 24 of 28
READING FROM THE AD7991/AD7995/AD7999
Reading data from the conversion result register is a 2-byte
operation, as shown in Figure 25. Therefore, a read operation
always involves two bytes.
After the AD7991/AD7995/AD7999 have received a read
address, any number of reads can be performed from the
conversion result register.
Following a start condition, the master writes the 7-bit address
of the AD7991/AD7995/AD7999 and then sets R/W to 1. The
AD7991/AD7995/AD7999 acknowledge this by pulling the
SDA line low. They then output the conversion result over the
I2C bus, preceded by four status bits. The status bits are two
leading 0s followed by the channel identifier bits. For the
AD7995 there are two trailing 0s, and for the AD7999 there are
four trailing 0s.
After the master has addressed the AD7991/AD7995/AD7999,
the part begins to power up on the ninth SCLK rising edge. At
the same time, the acquisition phase begins. When approximately
0.6 μs have elapsed, the acquisition phase ends. The input is
sampled and a conversion begins. This is done in parallel to the
read operation and should not affect the read operation. The
master reads back two bytes of data. On the ninth SCLK rising
edge of the second byte, if the master sends an ACK, it keeps
reading conversion results and the AD7991/AD7995/AD7999
powers up and performs a second conversion. If the master sends
a NO ACK, the AD7991/AD7995/AD7999 does not power up
on the ninth SCLK rising edge of the second byte. If a further
conversion is required, the part converts on the next channel, as
selected in the configuration register. See Table 11 for information
about the channel selection.
If the master sends a NO ACK on the ninth SCLK rising edge of
the second byte, the conversion is finished and no further
conversion is preformed.
To put the part into full shutdown mode, the user should issue a
stop condition to the AD7991/AD7995/AD7999. If the AD7991/
AD7995/AD7999 is not put into full shutdown mode, it will draw
a few tens of microamperes from the supply.
0
6461
-0
27
SDA
11
9
D10
D9
D8
A0
1
00
0
SCL
1
D11
1
D7
D6
D5
D2
D1
D0
D4
D3
SCL (CONTINUED)
SDA (CONTINUED)
CHID1 CHID0
R/W
9
START BY
MASTER
ACK BY
ADC
NO ACK BY
MASTER
ACK BY
MASTER
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM ADC
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM ADC
Figure 25. Reading Two Bytes of Data from the AD7991Conversion Result Register
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