參數(shù)資料
型號: AD7980ACPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 7/28頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 1MSPS SAR 10LFCSP
標(biāo)準(zhǔn)包裝: 5,000
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 10mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個偽差分,單極
Data Sheet
AD7980
Rev. C | Page 15 of 28
ANALOG INPUT
Figure 28 shows an equivalent circuit of the input structure of
the AD7980.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forward-
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case (for
example, an input buffer with a short circuit), the current
limitation can be used to protect the part.
06392-
014
REF
RIN
CIN
IN+
OR IN–
GND
D2
CPIN
D1
Figure 28. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN) can be modeled as a parallel combination of
capacitor, CPIN, and the network formed by the series connection of
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 and is a lumped component made up of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass
filter that reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7980 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7980 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7980. The noise coming from
the driver is filtered by the AD7980 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the external
filter, if one is used. Because the typical noise of the AD7980 is
47.3 V rms, the SNR degradation due to the amplifier is
+
=
2
3dB
2
)
(
2
π
47.3
log
20
N
LOSS
Ne
f
SNR
where:
f–3dB is the input bandwidth in MHz of the AD7980
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
For ac applications, the driver should have a THD
performance commensurate with the AD7980.
For multichannel multiplexed applications, the driver
amplifier and the AD7980 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier’s data sheet, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier
Typical Application
Very low noise, small and low power
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low noise
5 V single-supply, low power
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