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參數(shù)資料
| 型號(hào)： | AD7934BRU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/32頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 4CH 1.5MSPS 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，單極；2 個(gè)偽差分，單極 |
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AD7933/AD7934
Rev. B | Page 7 of 32
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted. fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS;
TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter1
AD7933
AD7934
Unit
Description
700
kHz min
CLKIN frequency
25.5
MHz max
tQUIET
30
ns min
Minimum time between end of read and start of next conversion, that is, the time from
when the data bus goes into three-state until the next falling edge of CONVST
t1
10
ns min
CONVST pulse width
t2
15
ns min
CONVST falling edge to CLKIN falling edge setup time
t3
50
ns max
CLKIN falling edge to BUSY rising edge
t4
0
ns min
CS to WR setup time
t5
0
ns min
CS to WR hold time
t6
10
ns min
WR pulse width
t7
10
ns min
Data setup time before WR
t8
10
ns min
Data hold after WR
t9
10
ns min
New data valid before falling edge of BUSY
t10
0
ns min
CS to RD setup time
t11
0
ns min
CS to RD hold time
t12
30
ns min
RD pulse width
30
ns max
Data access time after RD
3
ns min
Bus relinquish time after RD
50
ns max
Bus relinquish time after RD
t15
0
ns min
HBEN to RD setup time
t16
0
ns min
HBEN to RD hold time
t17
10
ns min
Minimum time between reads/writes
t18
0
ns min
HBEN to WR setup time
t19
10
ns min
HBEN to WR hold time
t20
40
ns max
CLKIN falling edge to BUSY falling edge
t21
15.7
ns min
CLKIN low pulse width
t22
7.8
ns min
CLKIN high pulse width
1 Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. All timing specifications are with a 25 pF load capacitance (see Figure 34, Figure 35, Figure 36, and Figure 37).
2 Minimum CLKIN for specified performance; with slower SCLK frequencies, performance specifications apply typically.
3 The time required for the output to cross 0.4 V or 2.4 V.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
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| AD7934BRU-REEL | 功能描述:IC ADC 12BIT 4CH 1.5MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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| AD7934BRUZ | 功能描述:IC ADC 12BIT 4CH 1.5MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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