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參數(shù)資料
| 型號： | AD7927BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 461K |
| 代理商： | AD7927BRU |
REV. 0
–18–
AD7927
that when writing to the AD7927 between these valid conversions,
the DOUT line will not be driven during the extra write operation,
as shown in Figure 19.
It is critical that an extra write operation as outlined above is
never issued between valid conversions when the AD7927 is
executing through a sequence function, as the falling edge of
CS
in the extra write would move the mux on to the next channel in
the sequence. This means when the next valid conversion takes
place, a channel result would have been missed.
MICROPROCESSOR INTERFACING
The serial interface on the AD7927 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7927 with some of the
more common microcontroller and DSP serial interface protocols.
AD7927 to TMS320C541
The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7927. The
CS
input allows easy interfacing between the TMS320C541 and
the AD7927 without any glue logic required. The serial port of
the TMS320C541 is set up to operate in burst mode with internal
CLKX0 (TX serial clock on serial port 0) and FSX0 (TX frame
sync from serial port 0). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM = 1, and
TXM = 1. The connection diagram is shown in Figure 20. It
should be noted that for signal processing applications, it is impera-
tive that the frame synchronization signal from the TMS320C541
provides equidistant sampling. The V
DRIVE
pin of the AD7927
takes the same supply voltage as that of the TMS320C541. This
allows the ADC to operate at a higher voltage than the serial
interface, i.e., TMS320C541, if necessary.
TMS320C541
*
CLKX
AD7927
*
CLKR
DR
DT
FSX
FSR
V
DD
SCLK
DOUT
DIN
CS
V
DRIVE
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 20. Interfacing to the TMS320C541
AD7927 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7927 without any glue logic required. The V
DRIVE
pin of
the AD7927 takes the same supply voltage as that of the
ADSP-218x. This allows the ADC to operate at a higher voltage
than the serial interface, i.e., ADSP-218x, if necessary.
The SPORT0 Control Register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 21. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in Alter-
nate Framing Mode and the SPORT Control Register is set up as
described. The frame synchronization signal generated on the TFS
is tied to
CS,
and as with all signal processing applications equi-
distant sampling is necessary. However, in this example the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling may not be achieved.
AD7927
*
ADSP-218x
*
SCLK
DR
RFS
TFS
DT
V
DD
SCLK
DOUT
CS
DIN
V
DRIVE
*
ADDITIONAL PINS REMOVED FOR CLARITY
Figure 21. Interfacing to the ADSP-218x
CS
t
QUIET
MIN
t
CYCLE
5 s MIN
1
16
1
16
1
16
SCLK
VALID DATA
VALID DATA
DOUT
POWER-UP
DIN
Figure 19. General Timing Diagram
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