參數(shù)資料
型號(hào)： AD7927BRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
中文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝： MO-153AC, TSSOP-20
文件頁(yè)數(shù)： 17/21頁(yè)
文件大?。?/td> 461K
代理商： AD7927BRU
REV. 0
AD7927
–17–
CS
SCLK
DOUT
DIN
t
3
t
2
t
9
t
4
DB11
6
t
7
t
10
t
5
t
11
t
8
t
QUIET
t
CONVERT
WRITE
SEQ
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
1
2
3
4
5
13
14
15
16
B
ADD2
ADD1
ADD0
DB10
DB2
DB1
DB0
THREE-
STATE
ZERO
3 IDENTIFICATION BITS
THREE-
STATE
Figure 17. Serial Interface Timing Diagram
CS
SCLK
DOUT
DIN
t
CONVERT
6
t
2
t
3
t
9
t
4
DB11
t
7
t
5
t
11
t
8
ZERO
V
IN
0
SEQUENCE 1
SEQUENCE 2
3 IDENTIFICATION BITS
THREE-
STATE
THREE-
STATE
1
2
3
4
5
13
14
15
16
ADD2
ADD1
ADD0
DB10
DB2
DB1
DB0
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
V
IN
5
V
IN
6
V
IN
7
t
10
C
Figure 18. Writing to Shadow Register Timing Diagram
SERIAL INTERFACE
Figure 17 shows the detailed timing diagram for serial interfacing
to the AD7927. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7927 during each conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. The track and hold will
go back into track on the 14th SCLK falling edge as shown in
Figure 17 at point B, except when the write is to the Shadow
Register, in which case the track and hold will not return to
track until the rising edge of
CS
, i.e., point C in Figure 18. On
the 16th SCLK falling edge the DOUT line will go back into
three-state. If the rising edge of
CS
occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the DOUT line
will go back into three-state and the Control Register will not be
updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge, as shown in Figure 17. Sixteen serial clock
cycles are required to perform the conversion process and to
access data from the AD7927. For the AD7927, the 12 bits of
data are preceded by a leading zero and the three channel address
bits ADD2 to ADD0, identifying which channel the result corre-
sponds to.
CS
going low provides the leading zero to be read in by
the microcontroller or DSP. The three remaining address bits and
data bits are then clocked out by subsequent SCLK falling edges
beginning with the first address bit ADD2, thus the first falling
clock edge on the serial clock has a leading zero provided and
also clocks out address bit ADD2. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB,
i.e., the WRITE bit, has been set to 1. If the Control Register is
programmed to use the Shadow Register, then the writing of
information to the Shadow Register will take place on all 16 SCLK
falling edges in the next serial transfer as shown for example on the
AD7927 in Figure 18. Two sequence options can be programmed
in the Shadow Register. If the user does not want to program a
second sequence, then the eight LSBs should be filled with zeros.
The Shadow Register will be updated upon the rising edge of
CS
and the track and hold will begin to track the first channel
selected in the sequence.
The 16-bit word read from the AD7927 will always contain a
leading zero, three channel address bits that the conversion
result corresponds to, followed by the 12-bit conversion result.
Writing Between Conversions
As outlined in the Operating Modes section, not less than 5
m
s
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at least
5
m
s should always be left between
CS
falling edges. Consider the
case when writing to the AD7927 to power it up from shutdown
prior to a valid conversion. The user must write to the part to tell
it to power up before it can convert successfully. Once the serial
write to power up has finished, one may wish to perform the con-
version as soon as possible and not have to wait a further 5
m
s
before bringing
CS
low for the conversion. In this case, as long
as there is a minimum of 5
m
s between each
valid
conversion, then
only the quiet time between the
CS
rising edge at the end of the
write to power up and the next
CS
falling edge for a valid con-
version needs to be met. Figure 19 illustrates this point. Note
相關(guān)PDF資料
PDF描述
AD7934 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7934BRU 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7933 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7933BRU 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7937 LC2MOS 8+4 Loading Dual 12-Bit DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7927BRU-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 200KSPS 12-BIT SERL 20TSSOP - Tape and Reel
AD7927BRU-REEL7 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 20-Pin TSSOP T/R
AD7927BRUZ 功能描述:IC ADC 12BIT 8CH 200KSPS 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
AD7927BRUZ 制造商:Analog Devices 功能描述:IC 12BIT ADC SMD 7927 TSSOP20
AD7927BRUZ-REEL 功能描述:IC ADC 12BIT 8CH W/SEQ 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個(gè)單端，雙極；8 個(gè)差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*