參數(shù)資料
型號(hào)： AD7920BRMZ-REEL7
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 250KSPS 8MSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 250k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 15mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
配用： EVAL-AD7920CBZ-ND - BOARD EVALUATION FOR AD7920
AD7910/AD7920
Rev. C | Page 18 of 24
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7910/AD7920 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 22 shows how, as the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over
time drops accordingly.
For example, if the AD7910/AD7920 is operated in a
continuous sampling mode with a throughput rate of 100 kSPS
and an SCLK of 5 MHz (VDD = 5 V), and the device is placed in
the power-down mode between conversions, the power
consumption is calculated as follows.
The power dissipation during normal mode is 15 mW (VDD = 5 V).
The power dissipation includes the power dissipated while the part
is entering power-down mode, the power dissipated during the
dummy conversion (when the part is exiting power-down mode
and powering up), and the power dissipated during conversion.
As mentioned in the power-down mode section, to enter
power-down mode, CS has to be brought high anywhere
between the second and tenth SCLK falling edge. Therefore, the
power consumption when entering power-down mode varies
depending on the number of SCLK cycles used. In this example,
five SCLK cycles are used to enter power-down mode. This
gives a time period of 5 × (1/fSCLK) = 1 μs.
The power-up time is 1 μs, which implies that only five SCLK
cycles are required to power up the part. However, CS has to
remain low until at least the tenth SCLK falling edge when
exiting power-down mode. This means that a minimum of nine
SCLK cycles have to be used to exit power-down mode and
power up the part.
So, if nine SCLK cycles are used, the time to power up the part
and exit power-down mode is 9 × (1/fSCLK) = 1.8 μs.
Finally, the conversion time is 16 × (1/fSCLK) = 3.2 μs.
Therefore, the AD7910/AD7920 can be said to dissipate 15 mW
for 3.2 μs + 1.8 μs + 1 μs = 6 μs during each conversion cycle. If
the throughput rate is 100 kSPS, the cycle time is 10 μs and the
average power dissipated during each cycle is (6/10) × (15 mW)
= 9 mW. The power dissipation when the part is in power-down
has not been taken into account because the shutdown current
is so low and it does not have any effect on the overall power
dissipation value.
If VDD = 3 V, SCLK = 5 MHz, and the device is again in power-
down mode between conversions, the power dissipation during
normal operation is 4.2 mW. Assuming the same timing
conditions as before, the AD7910/AD7920 can now be said to
dissipate 4.2 mW for 6 μs during each conversion cycle. With a
throughput rate of 100 kSPS, the average power dissipated
during each cycle is (6/10) × (4.2 mW) = 2.52 mW. Figure 22
shows the power vs. throughput rate when using the power-
down mode between conversions with both 5 V and 3 V
supplies.
Power-down mode is intended for use with throughput rates of
approximately 160 kSPS and under because at higher sampling
rates there is no power saving made by using the power-down
mode.
THROUGHPUT RATE (kSPS)
100
0.1
0
P
O
WE
R
(mW)
10
1
0.01
20
VDD = 5V, SCLK = 5MHz
VDD = 3V, SCLK = 5MHz
40
60
80
100
120
140
160
180
02976-022
Figure 22. Power vs. Throughput Rate
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