參數(shù)資料
型號(hào)： AD7877ACP-REEL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Touch Screen Controller
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC32
封裝： 5 X 5 MM, MO-220VHHD-2, LFCSP-32
文件頁數(shù)： 24/44頁
文件大?。?/td> 1002K
代理商： AD7877ACP-REEL
AD7877
Rev. A | Page 24 of 44
0
YES
NO
ONCE-ONLY
MODE
TIMER
FINISHED
START TIMER
NO
YES
*NOTE: SEE EXPLANATION IN TEXT
LIMIT COMPARISON
START FCD TIMER
UPDATE ALERT
ENABLE/STATUS
REGISTER
CONVERT
SELECTED CHANNEL
IS FCD
FINISHED
NO
YES
NO
YES
NO
YES
YES
NO
IS AVERAGING
FINISHED
WRITE RESULT TO
REGISTERS
ALERT
SOURCE
ENABLED
IS ACQUISITION
IS FCD
REQUIRED
START ACQUISITION TIMER
OUT-OF-LIMIT
ASSERT ALERT
OUTPUT*
YES
NO
YES
NO
SEQVALID
SELECT NEXT
CHANNEL
GOTO MODE 00
IN SEQUENCE
YES
IS
SCREEN
TOUCHED
NO
YES
YES
NO
SIIS STOPACQ
SIIS STOPACQ
NO
YES
YES
NO
IS
SCREEN STILL
TOUCHED
YES
STOUCHED
YES
NO
NO
NO
HOST PROGRAMS
AD7877 IN MODE 11
Figure 39. Master Mode Sequencer Operation
INTERRUPTS
Data Available Output (DAV)
The data available output (DAV) indicates that new ADC data is
available in the results registers. While the ADC is idle or is
converting, DAV is high. Once the ADC has finished converting
and new data has been written to the results registers, DAV goes
low. Taking DAV low to read the registers resets DAV to a high
condition. DAV is also reset, if a new conversion is started by
the AD7877 because the timer expired. The host should attempt
to read the results registers only while DAV is low.
0
CS
DAV
AD7877
STATUS
IDLE
SETUP
CONADC
NEW DATA
HRESULTS
IDLE
t
CONV
Figure 40. Operation of DAV Output
DAV is useful as a host interrupt in master mode. In this mode,
the host can program the AD7877 to automatically perform a
sequence of conversions, and can be interrupted by DAV at the
end of each conversion sequence.
When the on-board timer is programmed to perform automatic
conversions, a limited time is available to the host to read the
results registers before another sequence of conversions begins.
The DAV signal is reset high when the timer expires, and the
host should not access the results registers while DAV is high.
Figure 41 shows the worst-case timings for reading the results
registers after DAV has gone low. The timer is set at a minimum,
and the conversion sequence includes all eleven possible ADC
channels. t
1
is the time taken for acquisition and conversion on
one ADC channel. t
2
shows the minimum timer delay, which is
1024 clock periods. t
3
is the time taken to read all 11 result
registers. If the host wants to read all 11 registers, then it must
do so before the timer expires. t
4
is the maximum time allowable
between DAV going low and the host beginning to read the
results registers. If t
4
is exceeded, then all registers cannot be
read before the start of a new conversion, and incorrect data
could be read by the host.
0
DOUT
AD7877
STATUS
CHANNEL 11
CONVERSION AND
ACQUISITION
TIMER INTERVAL
CHNL
1
t
1
t
2
t
3
t
4
CS
DAV
Figure 41. Timing for Reads after DAV Goes Low
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