參數(shù)資料
型號(hào)： AD7859LASZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 8CH 200KSPS 44-MQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 100k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 30mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
產(chǎn)品目錄頁(yè)面： 779 (CN2011-ZH PDF)
AD7859/AD7859L
REV. A
–8–
AD7859/AD7859L ON-CHIP REGISTERS
The AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu-
ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for performing a full power-
down and a full self-calibration.
Extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7859/AD7859L contains a Control register, ADC output data register, Status register, Test register and 10 Cali-
bration registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test
and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit
word, or as two 8-bit bytes, depending on the logic level at the W/B pin. When W/B is high, the 16 bits are transferred on DB0 to
DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/B is low, DB8/HBEN assumes its HBEN functionality
and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB.
When writing to the AD7859/AD7859L in byte mode, the low byte must be written first followed by the high byte. The two MSBs
of the complete 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are writ-
ten to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy.
Table I. Write Register Addressing
ADDR1
ADDR0
Comment
0
This combination does not address any register.
0
1
This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.
1
0
This combination addresses the CALIBRATION REGISTERS. The 14 LSBs of data are written to the
selected calibration register.
1
This combination addresses the CONTROL REGISTER. The 14 LSBs of data are written to the control
register.
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. As with writing to the AD7859/AD7859L either word or byte mode can be used. When reading
from the calibration registers in byte mode, the low byte must be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un-
til the read selection bits are changed in the control register.
Table II. Read Register Addressing
RDSLT1
RDSLT0
Comment
0
All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-
up setting. There is always four leading zeros when reading from the ADC output data register.
0
1
All successive read operations are from the TEST REGISTER.
1
0
All successive read operations are from the CALIBRATION REGISTERS.
1
All successive read operations are from the STATUS REGISTER.
TEST
REGISTER
CALIBRATION
REGISTERS
STATUS
REGISTER
GAIN (1)
OFFSET (1)
DAC (8)
GAIN (1)
OFFSET (1)
GAIN (1)
01
10
11
00
01
10
11
CALSLT1, CALSLT0
DECODE
ADC OUTPUT
DATA REGISTER
00
RDSLT1, RDSLT0
DECODE
Figure 3. Read Register Hierarchy/Address Decoding
ADDR1, ADDR0
DECODE
TEST
REGISTER
CONTROL
REGISTER
GAIN (1)
OFFSET (1)
DAC (8)
GAIN (1)
OFFSET (1)
GAIN (1)
01
10
11
00
01
10
11
CALSLT1, CALSLT0
DECODE
CALIBRATION
REGISTERS
Figure 2. Write Register Hierarchy/Address Decoding
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