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參數(shù)資料
| 型號(hào)： | AD7856KR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 8CH 5V 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 285k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 89.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；4 個(gè)偽差分，單極 |
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AD7856
–4–
REV. A
TIMING SPECIFICATIONS1 (V
DD = 5 V; TA = TMIN to TMAX, unless otherwise noted. A Grade: fCLKIN = 6 MHz; K Grade: fCLKIN = 4 MHz.)
Limit at TMIN, TMAX
Parameter
A Version
K Version
Units
Description
fCLKIN
2
500
kHz min
Master Clock Frequency
6
4
MHz max
fSCLK
6
4
MHz max
t1
3
100
ns min
CONVST Pulsewidth
t2
50
ns max
CONVST
↓ to BUSY↑ Propagation Delay
tCONVERT
3.5
5.25
s max
Conversion Time = 20 tCLKIN
t3
–0.4 tSCLK
ns min
SYNC
↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
±0.4 t
SCLK
±0.4 t
SCLK
ns min/max
SYNC
↓ to SCLK↓ Setup Time (Continuous SCLK Input)
t4
4
30
50
ns max
Delay from
SYNC
↓ Until DOUT 3-State Disabled
t5
4
30
50
ns max
Delay from
SYNC
↓ Until DIN 3-State Disabled
t6
4
45
75
ns max
Data Access Time After SCLK
↓
t7
30
40
ns min
Data Setup Time Prior to SCLK
↑
t8
20
ns min
Data Valid to SCLK Hold Time
t9
0.4 tSCLK
ns min
SCLK High Pulsewidth
t10
0.4 tSCLK
ns min
SCLK Low Pulsewidth
t11
30
ns min
SCLK
↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
30/0.4 tSCLK
ns min/max
(Continuous SCLK)
t12
5
50
ns max
Delay from
SYNC
↑ Until DOUT 3-State Enabled
t13
90
ns max
Delay from
SCLK
↑ to DIN Being Configured as Output
t14
6
50
ns max
Delay from
SCLK
↑ to DIN Being Configured as Input
t15
2.5 tCLKIN
ns max
CAL
↑ to BUSY↑ Delay
t16
2.5 tCLKIN
ns max
CONVST
↓ to BUSY↑ Delay in Calibration Sequence
tCAL
41.7
62.5
ms typ
Full Self-Calibration Time, Master Clock Dependent
(250026 tCLKIN)
tCAL1
37.04
55.5
ms typ
Internal DAC Plus System Full-Scale Cal Time, Master
Clock Dependent (222228 tCLKIN)
tCAL2
4.63
6.94
ms typ
System Offset Calibration Time, Master Clock Dependent
(27798 tCLKIN)
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 V.
See Table X and timing diagrams for different interface modes and calibration.
2Mark/Space ratio for the master clock input is 40/60 to 60/40.
3The
CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5t
12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6t
14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 14, quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
Specifications subject to change without notice.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7856KR-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 285ksps 14-bit Serial 24-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:8 CH. 14-BIT 300 KSPS ADC I.C. - Tape and Reel |
| AD7856KRZ | 功能描述:IC ADC 14BIT 8CHAN 5V 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7858 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| AD7858AN | 功能描述:IC ADC 12BIT 8CH SRL 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7858ANZ | 功能描述:IC ADC 12BIT 8CHAN SRL 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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