參數(shù)資料
型號(hào)： AD7829BRZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT 8CH 2MSPS 28-SOIC
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 400
位數(shù)： 8
采樣率（每秒）： 2M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 36mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極
AD7822/AD7825/AD7829
Rev. C | Page 17 of 28
PARALLEL INTERFACE
The parallel interface of the AD7822/AD7825/AD7829 is eight
bits wide. Figure 26 shows a timing diagram illustrating the
operational sequence of the AD7822/AD7825/AD7829 parallel
interface. The multiplexer address is latched into the AD7822/
AD7825/AD7829 on the falling edge of the RD input. The on-
chip track-and-hold goes into hold mode on the falling edge of
CONVST, and a conversion is also initiated at this point. When
the conversion is complete, the end of conversion line (EOC)
pulses low to indicate that new data is available in the output
register of the AD7822/AD7825/AD7829. The EOC pulse stays
logic low for a maximum time of 110 ns.
However, the EOC pulse can be reset high by a rising edge
of RD. This EOC line can be used to drive an edge-triggered
interrupt of a microprocessor. CS and RD going low accesses
the 8-bit conversion result. It is possible to tie CS permanently
low and use only RD to access the data. In systems where the
part is interfaced to a gate array or ASIC, this EOC pulse can be
applied to the CS and RD inputs to latch data out of the AD7822/
AD7825/AD7829 and into the gate array or ASIC. This means
that the gate array or ASIC does not need any conversion status
recognition logic, and it also eliminates the logic required in the
gate array or ASIC to generate the read signal for the AD7822/
AD7825/AD7829.
CONVST
EOC
CS
RD
DB0 TO DB7
A0 TO A2
t1
t4
t5
t6
t7
t8
t3
t9
t10
t11
t12
t13
VALID
DATA
NEXT
CHANNEL
ADDRESS
t2
01
32
1-
0
27
Figure 26. AD7822/AD7825/AD7829 Parallel Port Timing
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