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參數(shù)資料
| 型號(hào)： | AD7829BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 8CH 2MSPS 28-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 36mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極 |
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AD7822/AD7825/AD7829
Rev. C | Page 5 of 28
TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications 40°C to +85°C, unless otherwise noted.
Table 2.
Parameter1,
5 V ± 10%
3 V ± 10%
Unit
Conditions/Comments
t1
420
ns max
Conversion time
t2
20
ns min
Minimum CONVST pulse width
t3
30
ns min
Minimum time between the rising edge of RD and the next falling edge of convert star
t4
110
ns max
EOC pulse width
70
ns min
t5
10
ns max
RD rising edge to EOC pulse high
t6
0
ns min
CS to RD setup time
t7
0
ns min
CS to RD hold time
t8
30
ns min
Minimum RD pulse width
t93
10
20
ns max
Data access time after RD low
t104
5
ns min
Bus relinquish time after RD high
20
ns max
t11
10
ns min
Address setup time before falling edge of RD
t12
15
ns min
Address hold time after falling edge of RD
t13
200
ns min
Minimum time between new channel selection and convert start
tPOWER UP
25
μs typ
Power-up time from rising edge of CONVST using on-chip reference
tPOWER UP
1
μs max
Power-up time from rising edge of CONVST using external 2.5 V reference
1 Sample tested to ensure compliance.
2 See Figure 24, Figure 25, and Figure 26.
3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and time required for an output
to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.
4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200A
IOL
200A
IOH
2.1V
TO OUTPUT
PIN
CL
50pF
013
21
-00
2
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
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