參數(shù)資料
型號(hào)： AD7792BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/33頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT SIG-DEL 3CH 16TSSOP
標(biāo)準(zhǔn)包裝： 96
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 779 (CN2011-ZH PDF)
配用： EVAL-AD7792EBZ-ND - BOARD EVALUATION FOR AD7792
AD7792/AD7793
Rev. B | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04
85
5-
00
5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
CS
IOUT1
AIN2(+)
AIN1(–)
AIN1(+)
SCLK
DOUT/RDY
DVDD
AVDD
REFIN(–)/AIN3(–)
AIN2(–)
REFIN(+)/AIN3(+)
IOUT2
GND
DIN
AD7792/
AD7793
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be
continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information being transmitted to or from the ADC in smaller batches of data.
2
CLK
Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can
be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a
common clock, allowing simultaneous conversions to be performed.
3
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC
in systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
4
IOUT1
Output of Internal Excitation Current Source. The internal excitation current source can be made available at
this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA.
Either IEXC1 or IEXC2 can be switched to this output.
5
AIN1(+)
Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(
).
6
AIN1(
)
Analog Input. AIN1(
) is the negative terminal of the differential analog input pair AIN1(+)/AIN1().
7
AIN2(+)
Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(
).
8
AIN2(
)
Analog Input. AIN2(
) is the negative terminal of the differential analog input pair AIN2(+)/AIN2().
9
REFIN(+)/AIN3(+)
Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and
REFIN(
). REFIN(+) can lie anywhere between AVDD and GND + 0.1 V. The nominal reference voltage
REFIN(+)
REFIN() is 2.5 V, but the part functions with a reference from 0.1 V to AVDD. Alternatively, this pin
can function as AIN3(+) where AIN3(+) is the positive terminal of the differential analog input pair
AIN3(+)/AIN3(
).
10
REFIN(
)/AIN3()
Negative Reference Input/Analog Input. REFIN(
) is the negative reference input for REFIN. This reference
input can lie anywhere between GND and AVDD
0.1 V. This pin also functions as AIN3(), which is the
negative terminal of the differential analog input pair AIN3(+)/AIN3(
).
11
IOUT2
Output of Internal Excitation Current Source. The internal excitation current source can be made available at
this pin. The excitation current source is programmable so that the current can be 10 μA, 210 μA, or 1 mA.
Either IEXC1 or IEXC2 can be switched to this output.
12
GND
Ground Reference Point.
13
AVDD
Supply Voltage, 2.7 V to 5.25 V.
14
DVDD
Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which
is between 2.7 V and 5.25 V. The DVDD voltage is independent of the voltage on AVDD; therefore, AVDD can
equal 5 V with DVDD at 3 V or vice versa.
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