參數(shù)資料
型號(hào): AD7738BRU-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/28頁(yè)
文件大小: 0K
描述: IC ADC 24BIT 8CH SIG-DEL 28TSSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 15.4k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
配用: EVAL-AD7738EBZ-ND - BOARD EVAL FOR AD7738
REV. 0
AD7738
–25–
Figure 16. Typical ADC Frequency Response
NORMALIZED INPUT FREQUENCY
(INPUT FREQUENCY
CONVERSION TIME)
0
0.1
10
1
GAIN
dB
–10
–20
–30
–40
–50
–60
CHOP = 1
a. Chopping Enabled
NORMALIZED INPUT FREQUENCY
(INPUT FREQUENCY
CONVERSION TIME)
0
0.1
1000
1
GAIN
dB
–10
–20
–30
–40
–50
–60
10
100
CHOP = 0
b. Chopping Disabled
Analog Inputs Voltage Range
The absolute input voltage range with input the buffer enabled
is restricted from AGND + 200 mV to AVDD – 300 mV, which
also places restrictions on the common-mode range. Care must
be taken in setting up the common-mode voltage and input
voltage range so that these limits are not exceeded, otherwise
there will be degradation in linearity performance.
The analog inputs on the AD7738 can accept either unipolar or
bipolar input voltage ranges. Bipolar input ranges do not imply
that the part can handle negative voltages with respect to system
ground on its analog inputs. Unipolar and bipolar signals on the
AIN(+) input are referenced to the voltage on the respective
AIN(–) input.
For example, if AINCOM is 2.5 V and CH0 is configured to
measure AIN0 – AINCOM, 0 V to 1.25 V, the input voltage
range on the AIN0 input is 2.5 V to 3.75 V. If CH0 is config-
ured to measure AIN0 – AINCOM,
±1.25 V, the input voltage
range on the AIN0 input is 1.25 V to 3.75 V.
Analog Inputs Extended Voltage Range
The AD7738 output data code span corresponds to the nominal
input voltage range. However, the correct operation of the ADC
is guaranteed within the min/max input voltage range.
When the CLAMP bit of the Mode register is set to 1, the
Channel Data register will be digitally clamped either to all
zeros or all ones when the analog input voltage goes outside
the nominal input voltage range.
As shown in Tables XIII and XIV, when CLAMP = 0, the data
reflect the analog input voltage outside the nominal voltage
range. In this case, the SIGN and OVR bits in the Channel
Status register should be considered along with the Data register
value to decode the actual conversion result.
Table XIII. Input Voltage Range
1.25 V, 16 Bits, CLAMP = 0
Input (V)
Data (Hex)
SIGN
OVR
+1.45000
147B
0
1
+1.25008
0001
0
1
+1.25004
0000
0
1
+1.25000
FFFF
0
+0.00004
8001
0
0.00000
8000
0
–0.00004
7FFF
1
0
–1.25000
0000
1
0
–1.25004
FFFF
1
–1.25008
FFFE
1
–1.45000
EB85
1
Table XIV. Input Voltage Range 0 V to 1.25 V, 16 Bits,
CLAMP = 0
Input (V)
Data (Hex)
SIGN
OVR
1.45000
28F5
0
1
1.25004
0001
0
1
1.25002
0000
0
1
1.25000
FFFF
0
0.00002
0001
0
0.00000
0000
0
–0.00002
0000
1
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