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參數(shù)資料
| 型號： | AD7716BPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 22BIT SIGMA-DELTA 44-PLCC |
| 標準包裝： | 1 |
| 位數(shù)： | 22 |
| 采樣率（每秒）： | 2.23k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
REV. A
–5–
AD7716
SLAVE MODE TIMING CHARACTERISTICS1, 2 (AV
DD = DVDD = +5 V
5%; AVSS = –5 V
5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Parameter
(B Version)
Units
Conditions/Comments
fCLKIN
3, 4
400
kHz min
CLKIN Frequency
8
MHz max
tr
5
40
ns max
Digital Output Rise Time. Typically 20 ns
tf
5
40
ns max
Digital Output Fall Time. Typically 20 ns
t23
1/fCLKIN
ns min
CASCIN Pulse Width
t24
50
ns min
SCLK Width
t25
125
ns min
SCLK Period
t26
1/fCLKIN +30
ns min
CASCIN High to RFS Setup Time
t27
30
ns min
RFS
Low to SCLK High Setup Time
t28
6
50
ns max
SCLK High to SDATA Valid Delay
t29
50
ns min
RFS
Hold Time After SCLK High
t30
7
50
ns max
SCLK High to SDATA High Impedance Delay
0
ns min
t31
60
ns max
SCLK High to CASCOUT High Delay.
t32
2/fCLKIN
ns max
CASCOUT Pulse Width
NOTES
1Sample tested at +25
°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 4.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with f
CLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz.
5Specified using 10% and 90% points on waveform of interest.
6t
28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t
30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Figure 4. Slave Mode Timing Diagram
t
31
CASCIN (I)
SDATA (O)
CASCOUT (O)
t
23
t
29
t
27
t
24
t
t
32
SCLK (I)
t
25
t
30
DB31
CH1
DB30
CH1
DB29
CH1
DB28
CH1
DB27
CH1
DB2
CH4
DB1
CH4
DB0
CH4
t
26
t
28
RFS (I)
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