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參數(shù)資料
| 型號： | AD7716BP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 22-Bit Data Acquisition System |
| 中文描述： | 4-CH 22-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 430K |
| 代理商： | AD7716BP |
REV. A
–5–
AD7716
SLAVE MODE TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V
6
5%; AV
SS
= –5 V
6
5%; AGND = DGND = 0 V;
f
CLKIN
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
DD
; unless otherwise noted)
Parameter
(B Version)
Units
Conditions/Comments
f
CLKIN3, 4
400
8
40
40
1/f
CLKIN
50
125
1/f
CLKIN
+30
30
50
50
50
0
60
2/f
CLKIN
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns max
CLKIN Frequency
t
r5
t
f5
t
23
t
24
t
25
t
26
t
27
t
286
t
29
t
307
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
SCLK Width
SCLK Period
CASCIN High to
RFS
Setup Time
RFS
Low to SCLK High Setup Time
SCLK High to SDATA Valid Delay
RFS
Hold Time After SCLK High
SCLK High to SDATA High Impedance Delay
t
31
t
32
SCLK High to CASCOUT High Delay.
CASCOUT Pulse Width
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 and 4.
3
CLKIN duty cycle range is 40% to 60%.
4
The AD7716 is production tested with f
CLKIN
at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz.
5
Specified using 10% and 90% points on waveform of interest.
6
t
28
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7
t
30
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Figure 4. Slave Mode Timing Diagram
t
31
CASCIN (I)
SDATA (O)
CASCOUT (O)
t
23
t
29
t
27
t
24
t
24
t
32
SCLK (I)
t
25
t
30
DB31
CH1
DB30
CH1
DB29
CH1
DB28
CH1
DB27
CH1
DB2
CH4
DB1
CH4
DB0
CH4
t
26
t
28
RFS (I)
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