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參數(shù)資料
| 型號： | AD7716BP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS 22-Bit Data Acquisition System |
| 中文描述： | 4-CH 22-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 430K |
| 代理商： | AD7716BP |
REV. A
AD7716
MASTER MODE TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= +5 V
6
5%; AV
SS
= –5 V
6
5%; AGND = DGND = 0 V;
f
CLKIN
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
DD
; unless otherwise noted)
–4–
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Units
Conditions/Comments
f
CLKIN3, 4
400
8
40
40
1/f
CLKIN
1/f
CLKIN
1/2f
CLKIN
+ 30
50
40
50
1/f
CLKIN
40
1/f
CLKIN
45
1/2f
CLKIN
+ 50
1/2f
CLKIN
+ 10
1/2f
CLKIN
+ 60
50
20
1/2f
CLKIN
+ 50
2/f
CLKIN
kHz min
MHz max
ns max
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns
ns max
ns
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns
CLKIN Frequency
t
r5
t
f5
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
166
t
177
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
CASCIN to
DRDY
Setup Time
DRDY
Low to SCLK Low Delay
CLKIN High to
DRDY
Low, SCLK Active,
RFS
Active
CLKIN High to SCLK High Delay
SCLK Width
SCLK Period
SCLK High to
RFS
High Delay
RFS
Pulse Width
SCLK High to SDATA Valid Delay
SCLK Low to SDATA High Impedance Delay
t
18
t
19
CLKIN High to
DRDY
High Delay
CLKIN High to
RFS
High Impedance, SCLK High Impedance
t
20
t
21
SCLK Low to CASCOUT High Delay
CASCOUT Pulse Width
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 1 and 3.
3
CLKIN duty cycle range is 40% to 60%.
4
The AD7716 is production tested with f
at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode.
5
Specified using 10% and 90% points on waveform of interest.
6
t
16
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Figure 3. Master Mode Timing Diagram
DB31
CH1
t
20
t
21
CASCIN (I)
SCLK (O)
RFS (O)
SDATA (O)
CASCOUT (O)
t
17
t
8
t
7
t
18
t
19
t
9
t
11
t
10
t
12
t
13
t
12
t
19
t
15
t
14
t
16
DB30
CH1
DB29
CH1
DB25
CH1
DB24
CH1
DB23
CH1
DB2
CH4
DB1
CH4
DB0
CH4
CLKIN (I)
DRDY (O)
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