參數(shù)資料
型號(hào)： AD7716
廠商： Analog Devices, Inc.
英文描述： 22-Bit Data Acquisition System(LC2MOS 22位數(shù)據(jù)采集系統(tǒng))
中文描述： 22位數(shù)據(jù)采集系統(tǒng)（LC2MOS 22位數(shù)據(jù)采集系統(tǒng)）
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 439K
代理商： AD7716
REV. A
AD7716
–14–
MICROPROCESSOR INTERFACING
Interfacing the AD7716 to the ADSP-2100 Family
The ADSP-2100 family of microcomputers from Analog De-
vices are high speed, high performance digital signal processors.
Many members of the family have serial ports (known as
SPORTs) which are compatible with the AD7716. These in-
clude the ADSP-2101, ADSP-2105, ADSP-2111 and ADSP-
2115. Full details of these are available in the
ADSP-2100
Family User’s Manual
available from Analog Devices.
Figure 8 shows the hardware interface between two AD7716s
and SPORT 0 of the ADSP-2101 DSP. This yields a very effi-
cient 8-channel data acquisition system. The AD7716 is set up
for slave interface mode by tying the MODE pin high. This
means that the ADSP-2101 is the master in the system and sup-
plies the necessary frame synchronization and SCLK Signals to
the AD7716s when writing to and reading from the device.
On power up, the user should write to the AD7716 control reg-
ister in order to set the filter cutoff frequencies. The appropri-
ate SPORT 0 Control Register (0
3
3FF6) setting is “7EC7.”
This sets the transmit section for alternate inverted framing with
a word length of 8 bits. Two 8-bit words should then be written
to each AD7716 to program the filter cutoff frequencies. The
control register programming model is given in Table II. Note
that the LSB (DB0) must be loaded first as in the timing dia-
gram of Figure 2.
When the write operation is complete, a reset pulse should be
applied to both devices. This ensures that the sampling and in-
terface timing of the device are synchronized. The reset can be
under DSP control, in which case a flag output could be used.
After reset, the processor should jump to the read routine. For
this read routine, there are several registers that need to be set.
The SPORT0 Control Register setting is “7FCF.” This sets the
receive section for internal SCLK, continuous receive with al-
ternate inverted framing.
The SPORT0 SCLKDIV Register (0
3
3FF5) determines the
SCLK frequency from the ADSP-2101. With “0000” loaded,
the SCLK output is at its maximum (1/2 the master clock of
12.5 MHz).
In normal operation, a SPORT generates an interrupt when it
has received a data word. Autobuffering provides a mechanism
for receiving or transmitting an entire block of serial data before
an interrupt is generated. Service routines can operate on the
entire block of data, rather than on a single word, reducing over-
head significantly. This is ideal for use with a device like the
AD7716 where there is a requirement to read many bits of data
(256 in this case) for each sampling instant. The SPORT0
Autobuffer Control Register (0
3
3FF3) is loaded with “0001”
to enable the Receive Autobuffering.
The SPORT0 RFSDIV Register (0
3
3FF4) should be set to
the minimum value of “000F.” Finally the IRQ2 interrupt
should be enabled.
The DSP will now wait for an interrupt from the AD7716. This
interrupt is generated by the AD7716
DRDY
line going low. If
the interrupt service routine is set for autobuffered mode with a
length of 16 (16-bit) words, then the DSP will read in the 256
bits from the two AD7716s in one continuous stream and then
stop. The data from the two devices will be contained in the
designated data memory area and the DSP can now go and op-
erate on this as is necessary. Note that, because of the ADSP-
2101 framing, a one-bit shift left will be necessary on the data in
memory. For 16 data words, this will require 22 instruction
cycles.
ADSP-2101
CASCIN
A0 A1 A2
RESET
CASCOUT
MODE
TFS
SDATA
RFS
SCLK
AD7716 #1
CASCIN
A0
A1 A2
RESET
SDATA
SCLK
AD7716 #2
RESET
CONTROL
+5V
+5V
SCLK
TFS
DT
DR
IRQ2
(–VE EDGE TRIGGERED)
RFS
DRDY
TFS
RFS
DRDY
CASCOUT
MODE
+5V
4.7k
4.7k
+5V
Figure 8. 8-Channel Data Acquisition System Using the ADSP-2101 Digital Signal Processor
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