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參數(shù)資料
| 型號： | AD7711ASQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC with RTD Current Source |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERDIP-24 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 222K |
| 代理商： | AD7711ASQ |
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2
AD7711A
–23–
REV. C
Figure 13b shows a timing diagram for a write operation to the
AD7711A with
TFS
returning high during the write operation
and returning low again to write the rest of the data word. Tim-
ing parameters and functions are very similar to that outlined for
Figure 13a but Figure 13b has a number of additional times to
show timing relationships when
TFS
returns high in the middle
of transferring a word.
Data to be loaded to the AD7711A must be valid prior to the
rising edge of the SCLK signal.
TFS
should return high during
the low time of SCLK. After
TFS
returns low again, the next bit
of the data word to be loaded to the AD7711A is clocked in on
next high-level of the SCLK input. On the last high time of the
SCLK input, the LSB is loaded to the AD7711A.
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY
line and the write operation does not have any effect
on the status of
DRDY
. A write operation to the control register
or the calibration register must always write 24 bits to the
respective register.
Figure 13a shows a write operation to the AD7711A with
TFS
remaining low for the duration of the write operation. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must re-
main valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7711A
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7711A on the high level of
this SCLK signal with the MSB transferred first. On the last
active high time of SCLK, the LSB is loaded to the AD7711A.
t
32
t
35
t
36
t
27
t
26
t
33
t
34
MSB
LSB
SDATA (I)
SCLK (I)
TFS
(I)
A0 (I)
Figure 13a. External-Clocking Mode, Control/Calibration Register Write Operation
SDATA (I)
SCLK (I)
TFS
(I)
A0 (I)
t
32
t
26
t
30
t
35
t
36
t
27
MSB
BIT N
BIT N+1
t
35
t
36
Figure 13b. External-Clocking Mode, Control/Calibration Register Write Operation (
TFS
Returns High
During Write Operation)
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相關代理商/技術參數(shù) |
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| AD7712AN | 功能描述:IC ADC SIGNAL COND LC2MOS 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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