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參數(shù)資料
| 型號： | AD7711AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC with RTD Excitation Currents |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MO-095AG, DIP-24 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 242K |
| 代理商： | AD7711AN |
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REV. F
–18–
AD7711
After the zero-scale point is calibrated, the full-scale point is
applied and the second step of the calibration process is initiated
by again writing the appropriate values (0, 1, 1) to MD2, MD1
and MD0. Again the full-scale voltage must be set up before the
calibration is initiated and it must remain stable throughout the
calibration step.
DRDY
goes low at the end of this second step
to indicate that the system calibration is complete. In the unipo-
lar mode, the system calibration is performed between the two
endpoints of the transfer function; in the bipolar mode, it is
performed between midscale and positive full scale.
This two-step system calibration mode offers another feature.
After the sequence has been completed, additional offset or gain
calibrations can be performed by themselves to adjust the zero
reference point or the system gain. This is achieved by perform-
ing the first step of the system calibration sequence (by writing
0, 1, 0 to MD2, MD1, MD0). This will adjust the zero-scale or
offset point but will not change the slope factor from what was
set during a full system calibration sequence.
System calibration can also be used to remove any errors from
an antialiasing filter on the analog input. A simple R, C anti-
aliasing filter on the front end may introduce a gain error on the
analog input voltage but the system calibration can be used to
remove this error.
System Offset Calibration
System offset calibration is a variation of both the system cali-
bration and self-calibration. In this case, the zero-scale point
for the system is presented to the AIN input of the converter.
System-offset calibration is initiated by writing 1, 0, 0 to MD2,
MD1, MD0. The system zero-scale coefficient is determined by
converting the voltage applied to the AIN input, while the full-
scale coefficient is determined from the span between this AIN
conversion and a conversion on V
REF
. The zero-scale point
should be applied to the AIN input for the duration of the cali-
bration sequence. This is a one-step calibration sequence with
DRDY
going low when the sequence is completed. In the uni-
polar mode, the system offset calibration is performed between
the two end points of the transfer function; in the bipolar mode,
it is performed between midscale and positive full scale.
Background Calibration
The AD7711 also offers a background calibration mode where
the part interleaves its calibration procedure with its normal
conversion sequence. In the background calibration mode, the
same voltages are used as the calibration points as are used in
Table VI. Calibration Truth Table
Cal Type
MD2, MD1, MD0
Zero-Scale Cal
Full-Scale Cal
Sequence
Duration
9
×
1/Output Rate
4
×
1/Output Rate
4
×
1/Output Rate
9
×
1/Output Rate
6
×
1/Output Rate
Self-Cal
System Cal
System Cal
System Offset Cal
Background Cal
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
Shorted Inputs
AIN
–
AIN
Shorted Inputs
V
REF
–
AIN
V
REF
V
REF
One Step
Two Step
Two Step
One Step
One Step
the self-calibration mode, i.e., shorted inputs and V
REF
. The
background calibration mode is invoked by writing 1, 0, 1 to
MD2, MD1, MD0 of the control register. When invoked, the
background calibration mode reduces the output data rate of the
AD7711 by a factor of six while the –3 dB bandwidth remains
unchanged. Its advantage is that the part is continually perform-
ing calibration and automatically updating its calibration coeffi-
cients. As a result, the effects of temperature drift, supply
sensitivity and time drift on zero and full-scale errors are auto-
matically removed. When the background calibration mode is
turned on, the part will remain in this mode until bits MD2,
MD1 and MD0 of the control register are changed. With back-
ground calibration mode on, the first result from the AD7711
will be incorrect as the full-scale calibration will not have been
performed. For a step change on the input, the second output
update will have settled to 100% of the final value.
Table VI summarizes the calibration modes and the calibration
points associated with them. It also gives the duration from
when the calibration is invoked to when valid data is available to
the user.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits on
the amount of offset and span that can be accommodated. The
range of input span in both the unipolar and bipolar modes has
a minimum value of 0.8
×
V
REF
/GAIN and a maximum value of
2.1
×
V
REF
/GAIN.
The amount of offset which can be accommodated depends on
whether the unipolar or bipolar mode is being used. This offset
range is limited by the requirement that the positive full-scale
calibration limit is
≤
1.05
×
V
REF
/GAIN. Therefore, the offset
range plus the span range cannot exceed 1.05
×
V
REF
/GAIN. If
the span is at its minimum (0.8
×
V
REF
/GAIN) the maximum
the offset can be is (0.25
×
V
REF
/GAIN).
In the bipolar mode, the system offset calibration range is again
restricted by the span range. The span range of the converter in
bipolar mode is equidistant around the voltage used for the
zero-scale point thus the offset range plus half the span range
cannot exceed (1.05
×
V
REF
/GAIN). If the span is set to
2 ×
V
REF
/
GAIN, the offset span cannot move more than
±
(0.05
×
V
REF
/
GAIN) before the endpoints of the transfer function exceed the
input overrange limits
±
(1.05
×
V
REF
/GAIN). If the span range
is set to the minimum
±
(0.4
×
V
REF
/GAIN) the maximum
al-
lowable offset range is
±
(0.65
×
V
REF
/GAIN).
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| AD7711ANZ | 功能描述:IC ADC 24BIT RTD I SOURCE 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7711ANZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
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