參數(shù)資料
型號(hào): AD7711A*
廠商: Analog Devices, Inc.
英文描述: LC2MOS Signal Conditioning ADC with RTD Current Source
中文描述: LC2MOS信號(hào)調(diào)理ADC的電流源電阻
文件頁數(shù): 23/27頁
文件大小: 222K
2
AD7711A
–23–
REV. C
Figure 13b shows a timing diagram for a write operation to the
AD7711A with
TFS
returning high during the write operation
and returning low again to write the rest of the data word. Tim-
ing parameters and functions are very similar to that outlined for
Figure 13a but Figure 13b has a number of additional times to
show timing relationships when
TFS
returns high in the middle
of transferring a word.
Data to be loaded to the AD7711A must be valid prior to the
rising edge of the SCLK signal.
TFS
should return high during
the low time of SCLK. After
TFS
returns low again, the next bit
of the data word to be loaded to the AD7711A is clocked in on
next high-level of the SCLK input. On the last high time of the
SCLK input, the LSB is loaded to the AD7711A.
Write Operation
Data can be written to either the control register or calibration
registers. In either case, the write operation is not affected by
the
DRDY
line and the write operation does not have any effect
on the status of
DRDY
. A write operation to the control register
or the calibration register must always write 24 bits to the
respective register.
Figure 13a shows a write operation to the AD7711A with
TFS
remaining low for the duration of the write operation. A0 deter-
mines whether a write operation transfers data to the control
register or to the calibration registers. This A0 signal must re-
main valid for the duration of the serial write operation. As
before, the serial clock line should be low between read and
write operations. The serial data to be loaded to the AD7711A
must be valid on the high level of the externally applied SCLK
signal. Data is clocked into the AD7711A on the high level of
this SCLK signal with the MSB transferred first. On the last
active high time of SCLK, the LSB is loaded to the AD7711A.
t
32
t
35
t
36
t
27
t
26
t
33
t
34
MSB
LSB
SDATA (I)
SCLK (I)
TFS
(I)
A0 (I)
Figure 13a. External-Clocking Mode, Control/Calibration Register Write Operation
SDATA (I)
SCLK (I)
TFS
(I)
A0 (I)
t
32
t
26
t
30
t
35
t
36
t
27
MSB
BIT N
BIT N+1
t
35
t
36
Figure 13b. External-Clocking Mode, Control/Calibration Register Write Operation (
TFS
Returns High
During Write Operation)
相關(guān)PDF資料
PDF描述
AD7711AN LC2MOS Signal Conditioning ADC with RTD Excitation Currents
AD7711AQ LC2MOS Signal Conditioning ADC with RTD Excitation Currents
AD7711AR LC2MOS Signal Conditioning ADC with RTD Excitation Currents
AD7711SQ LC2MOS Signal Conditioning ADC with RTD Excitation Currents
AD7711* LC2MOS Signal Conditioning ADC with RTD Excitation Currents
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